Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

The authors propose two fault-tolerance techniques for hybrid CMOS/nanoarchitecture implementing logic functions as look-up tables. The authors compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, the authors implement a combined two-dimensional coding scheme using Hamming and Bose-Chaudhuri-Hocquenghem (BCH) codes to address fault rates greater than 5. In the second technique, Hamming coding is complemented with bad line exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20). The authors have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don-t Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain

A survey of fault-tolerance algorithms for reconfigurable nano-crossbar arrays

ACM Comput. Surv. Volume 50, issue 6 (November 2017)Nano-crossbar arrays have emerged as a promising and viable technology to improve computing performance of electronic circuits beyond the limits of current CMOS. Arrays offer both structural efficiency with reconfiguration and prospective capability of integration with different technologies. However, certain problems need to be addressed, and the most important one is the prevailing occurrence of faults. Considering fault rate projections as high as 20% that is much higher than those of CMOS, it is fair to expect sophisticated fault-tolerance methods. The focus of this survey article is the assessment and evaluation of these methods and related algorithms applied in logic mapping and configuration processes. As a start, we concisely explain reconfigurable nano-crossbar arrays with their fault characteristics and models. Following that, we demonstrate configuration techniques of the arrays in the presence of permanent faults and elaborate on two main fault-tolerance methodologies, namely defect-unaware and defect-aware approaches, with a short review on advantages and disadvantages. For both methodologies, we present detailed experimental results of related algorithms regarding their strengths and weaknesses with a comprehensive yield, success rate and runtime analysis. Next, we overview fault-tolerance approaches for transient faults. As a conclusion, we overview the proposed algorithms with future directions and upcoming challenges.This work is supported by the EU-H2020-RISE project NANOxCOMP no 691178 and the TUBITAK-Career project no 113E760

A reconfiguration-based defect-tolerant design paradigm for nanotechnologies

textEntering the nanometer era, a major challenge to current design method ologies and tools is how to effectively address the high defect densities pro jected for emerging nanotechnologies. To this end, in this dissertation we propose a reconfiguration-based defect-tolerant design paradigm for defect prone nanoelectronic technologies. In our paradigm, designs are mapped into a nanofabric comprised of reconfigurable regions, architected using a suitable hierarchy of design abstractions, so as to meet the target yield with best ex pected performance. The new design goal is thus to devise an appropriate structural/behavioral decomposition which improves scalability by constrain ing the defect mapping and reconfiguration process to small fabric regions, while meeting a desired probability of successful instantiation, i.e., yield. A key feature of our proposed nanofabric architecture is that it en ables the defect mapping and configuration tasks to be performed within the nanofabric itself, eliminating the costly per-chip offline processing. Specifically, we have devised a novel group testing method that can systematically identify defective components and/or connectivity in a fabric region. It enables the entire fabric to be tested and configured in a scalable way, using a relatively small number of easily configured triple-modular-redundancy (TMR) test tiles executing concurrently on different regions of the target nanofabric. Moreover, our proposed design paradigm offers a rich framework in which critical trade-offs among performance, yield, and complexity can be explored. The probabilistic nature of these tradeoffs has required us to in troduce a new class of ‘reliability-aware’ high-level synthesis (HLS) problems. In particular, rather than carefully optimizing a single (‘deterministic’) solu tion, as done in traditional HLS, our approach requires the joint synthesis and optimization of a sufficiently large family of alternative solutions, so as to achieve the specified target yield, with best-expected performance. We have developed a Reliability-Aware Synthesis framework for NANOfabrics (RAS NANO), aimed at systematically solving this new class of ‘reliability-aware’ HLS problem. It enables designers to effectively explore the complex prob abilistic design space associated with the new reconfiguration-based defect tolerant design paradigm.Electrical and Computer Engineerin