A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

A Novel Differential Ramp Generator Circuit with PVT Compensation Structure

Applications like counter ADC demanded accurate ramp signal with low power dissipation. This paper presents a novel approach of low power differential ramp generator with negative feedback for the compensation of the variations in process, voltage, and temperature (PVT). The derived equations of the proposed ramp generator circuit show that PVT compensation is enhanced significantly. Additionally, the circuit design and simulations were done in TSMC 0.18-μm CMOS technology. The Monte Carlo simulation results and corner analysis show that the linearity of the ramp signal is about 9-bit while power dissipation of the circuit is about 2.61μW

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

Low-power adaptive control scheme using switching activity measurement method for reconfigurable analog-to-digital converters

Power consumption is a critical issue for portable devices. The ever-increasing demand for multimode wireless applications and the growing concerns towards power-aware green technology make dynamically reconfigurable hardware an attractive solution for overcoming the power issue. This is due to its advantages of flexibility, reusability, and adaptability. During the last decade, reconfigurable analog-to-digital converters (ReADCs) have been used to support multimode wireless applications. With the ability to adaptively scale the power consumption according to different operation modes, reconfigurable devices utilise the power supply efficiently. This can prolong battery life and reduce unnecessary heat emission to the environment. However, current adaptive mechanisms for ReADCs rely upon external control signals generated using digital signal processors (DSPs) in the baseband. This thesis aims to provide a single-chip solution for real-time and low-power ReADC implementations that can adaptively change the converter resolution according to signal variations without the need of the baseband processing. Specifically, the thesis focuses on the analysis, design and implementation of a low-power digital controller unit for ReADCs. In this study, the following two important reconfigurability issues are investigated: i) the detection mechanism for an adaptive implementation, and ii) the measure of power and area overheads that are introduced by the adaptive control modules. This thesis outlines four main achievements to address these issues. The first achievement is the development of the switching activity measurement (SWAM) method to detect different signal components based upon the observation of the output of an ADC. The second achievement is a proposed adaptive algorithm for ReADCs to dynamically adjust the resolution depending upon the variations in the input signal. The third achievement is an ASIC implementation of the adaptive control module for ReADCs. The module achieves low reconfiguration overheads in terms of area and power compared with the main analog part of a ReADC. The fourth achievement is the development of a low-power noise detection module using a conventional ADC for signal improvement. Taken together, the findings from this study demonstrate the potential use of switching activity information of an ADC to adaptively control the circuits, and simultaneously expanding the functionality of the ADC in electronic systems

Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters

Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation

X-Band LLRF Developments for High Power CLIC Test Stands and Waveguide Interferometry for Phase Stabilisation

This thesis describes the upgrade of the first high power X-band RF test for high gradient accelerating structures at CERN, as required for the e+ e- collider research program; Compact Linear Collider, CLIC. Significant improvements to the control system and operation of the first test stand, Xbox-1, are implemented. The design and commissioning of the new Low Level Radio Frequency, LLRF, system is described in detail. The upgrade also encompasses software, interlock systems, timing, safety and control. The new LLRF requires an up-convertor to convert an input signal at 187.4 MHz to 11.806 GHz. The most common method is a phase locked loop, PLL, an alternative method was envisioned which uses single side-band up-convertor. This necessitated the design and manufacture of a custom cavity filter. The up-convertor and PLL are compared and both are implemented in the new LLRF. The new LLRF system is implemented at Xbox1 and used to RF condition a 50 MW CPI klystron, the final output power was 45 MW for a 50 ns RF pulse length. The phase and amplitude of the LLRF, TWT and klystron are characterised with both the PLL and up-convertor. The klystron phase stability was studied using a sensitivity analysis. The waveguide network between the klystron and the accelerating structures is approximately 30 m. This network is subject to environmental phase changes which affect the phase stability of the RF arriving at the structures. A single path inteferometer was designed which will allow a phase measurement pulse at a secondary frequency to be injected into the waveguide network interleaved with klystron pulses. The interferometer is commissioned in the lab and low power measurements validate its operation. The system is then integrated into the high power network at Xbox1 and used to measure phase shifts in the waveguide network which are correlated with temperature