Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops

This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed

Design of a 3 GHz fine resolution LC DCO

In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin

An all-digital ΣΔ--frequency discriminator of arbitrary order

In this paper, we propose an all-digital frequency synthesizer architecture, based on an all-digital ΣΔ-frequency discriminator. The new all-digital synthesizer is compared to previously published work. The architecture of the ΣΔ-frequency discriminator is verified using behavioral simulation

차량용 CIS Interface 를 위한 All-Digital Phase-Locked Loop 의 설계 및 분석

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 정덕균.This thesis presents design techniques for All-Digital Phase-Locked Loop (ADPLL) assisting the automotive CMOS image sensor (CIS) interface. To target Gear 3 of the automotive physical system, the proposed AD-PLL has a wide operation range, low RMS jitter, and high PVT tolerance characteristics. Detailed analysis of the loop dynamics and the noise analysis of AD-PLL are done by using Matlab and Verilog behavioral modeling simulation before an actual design. Based on that analysis, the optimal DLF gain configurations are yielded, and also, accurate output responses and performance are predictable. The design techniques to reduce the output RMS jitter are discussed thoroughly and utilized for actual implementation. The proposed AD-PLL is fabricated in the 40 nm CMOS process and occupies an effective area of 0.026 mm2. The PLL output clock pulses exhibit an RMS jitter of 827 fs at 2 GHz. The power dissipation is 5.8 mW at 2 GHz, where the overall supply voltage domain is 0.9 V excluding the buffer which is 1.1 V domain.본 논문에서는 자동차 CMOS 이미지 센서 (CIS) 인터페이스를 지원하 는 AD-PLL 을 제안한다. Automotive Physical 시스템의 Gear 3 를 지원하기 위해 제안된 AD-PLL 은 1.5 GHz 에서 3 GHz 의 동작 주파수를 가지며, 낮 은 RMS Jitter 및 PVT 변화에 대한 높은 둔감성을 갖는다. 설계에 앞서서 Matlab 및 Verilog Behavioral Simulation 을 통해 Loop system 의 역학에 대한 자세한 분석 및 AD-PLL 의 Noise 분석을 수행하였고, 이 분석을 기반으로 최적의 DLF gain 과 정확한 출력 응답 및 성능을 예측 할 수 있었다. 또한, 출력의 Phase Noise 와 RMS Jitter 를 줄이기 위한 설계 기법을 자세히 다루고 있으며 이를 실제 구현에 활용했다. 제안된 회로는 40 nm CMOS 공정으로 제작되었으며 Decoupling Cap 을 제외하고 0.026 mm2 의 유효 면적을 차지한다. 측정된 출력 Clock 신호의 RMS Jitter 값은 2 GHz 에서 827 fs 이며, 총 5.8 mW의 Power 를 소비한다. 이 때, 전체적인 공급 전압은 0.9 V 이며, Buffer 의 Power 만이 1.1 V 를 사용하 였다.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON ALL-DIGITAL PLL 4 2.1 OVERVIEW 4 2.2 BUILDING BLOCKS OF AD-PLL 7 2.2.1 TIME-TO-DIGITAL CONVERTER 7 2.2.2 DIGITALLY-CONTROLLED OSCILLATOR 10 2.2.3 DIGITAL LOOP FILTER 13 2.2.4 DELTA-SIGMA MODULATOR 16 2.3 PHASE NOISE ANALYSIS OF AD-PLL 20 2.3.1 BASIC ASSUMPTION OF LINEAR ANALYSIS 20 2.3.2 NOISE SOURCES OF AD-PLL 21 2.3.3 EFFECTS OF LOOP DELAY ON AD-PLL 24 2.3.4 PHASE NOISE ANALYSIS OF PROPOSED AD-PLL 26 CHAPTER 3 DESIGN OF ALL-DIGITAL PLL 28 3.1 DESIGN CONSIDERATION 28 3.2 OVERALL ARCHITECTURE 30 3.3 CIRCUIT IMPLEMENTATION 32 3.3.1 PFD-TDC 32 3.3.2 DCO 37 3.3.3 DIGITAL BLOCK 43 3.3.4 LEVEL SHIFTING BUFFER AND DIVIDER 45 CHAPTER 4 MEASUREMENT AND SIMULATION RESULTS 52 4.1 DIE PHOTOMICROGRAPH 52 4.2 MEASUREMENT SETUP 54 4.3 TRANSIENT ANALYSIS 57 4.4 PHASE NOISE AND SPUR PERFORMANCE 59 4.4.1 FREE-RUNNING DCO 59 4.4.2 PLL PERFORMANCE 61 4.5 PERFORMANCE SUMMARY 65 CHAPTER 5 CONCLUSION 67 BIBLIOGRAPHY 68 초 록 72Maste

An Analog Phase Interpolation Based Fractional-N PLL

A novel phase-locked loop topology is presented. Compared to conventional designs, this architecture aims to increase frequency resolution and reduce quantization noise while maintaining the fractional-N benefits of high bandwidth and low phase noise up-conversion. This is achieved utilizing a feedforward mechanism for offset cancellation from the integer-N frequency. The design is implemented in a 0.13μm CMOS process technology. A frequency resolution of 1.16Hz is achieved on a 5GHz differential delay cell VCO with a 100MHz reference oscillator. A ping-pong swallow counter topology alleviates pipeline latency to achieve 1-64 divide ratios. A digital pulse generator and nested phase-frequency detector provide tunable offset cancellation. A 5-bit current-steering DAC capable of 200ps pulses reduces output spurs. Theoretical calculations and Simulink modeling provides insight to the effects of non idealities in the system. Test structures and loop configurability are programmed via SPI interface through a custom GUI and prototype PCB

통계적 주파수 검출기 기반 기준 주파수를 사용하지 않는 클록 및 데이터 복원 회로의 설계 방법론

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.In this thesis, a design of a high-speed, power-efficient, wide-range clock and data recovery (CDR) without a reference clock is proposed. A frequency acquisition scheme using a stochastic frequency detector (SFD) based on the Alexander phase detector (PD) is utilized for the referenceless operation. Pat-tern histogram analysis is presented to analyze the frequency acquisition behavior of the SFD and verified by simulation. Based on the information obtained by pattern histogram analysis, SFD using autocovariance is proposed. With a direct-proportional path and a digital integral path, the proposed referenceless CDR achieves frequency lock at all measurable conditions, and the measured frequency acquisition time is within 7μs. The prototype chip has been fabricated in a 40-nm CMOS process and occupies an active area of 0.032 mm2. The proposed referenceless CDR achieves the BER of less than 10-12 at 32 Gb/s and exhibits an energy efficiency of 1.15 pJ/b at 32 Gb/s with a 1.0 V supply.본 논문은 기준 클럭이 없는 고속, 저전력, 광대역으로 동작하는 클럭 및 데이터 복원회로의 설계를 제안한다. 기준 클럭이 없는 동작을 위해서 알렉산더 위상 검출기에 기반한 통계적 주파수 검출기를 사용하는 주파수 획득 방식이 사용된다. 통계적 주파수 검출기의 주파수 추적 양상을 분석하기 위해 패턴 히스토그램 분석 방법론을 제시하였고 시뮬레이션을 통해 검증하였다. 패턴 히스토그램 분석을 통해 얻은 정보를 바탕으로 자기공분산을 이용한 통계적 주파수 검출기를 제안한다. 직접 비례 경로와 디지털 적분 경로를 통해 제안된 기준 클럭이 없는 클럭 및 데이터 복원회로는 모든 측정 가능한 조건에서 주파수 잠금을 달성하는 데 성공하였고, 모든 경우에서 측정된 주파수 추적 시간은 7μs 이내이다. 40-nm CMOS 공정을 이용하여 만들어진 칩은 0.032 mm2의 면적을 차지한다. 제안하는 클럭 및 데이터 복원회로는 32 Gb/s의 속도에서 비트에러율 10-12 이하로 동작하였고, 에너지 효율은 32Gb/s의 속도에서 1.0V 공급전압을 사용하여 1.15 pJ/b을 달성하였다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 13 CHAPTER 2 BACKGROUNDS 14 2.1 CLOCKING ARCHITECTURES IN SERIAL LINK INTERFACE 14 2.2 GENERAL CONSIDERATIONS FOR CLOCK AND DATA RECOVERY 24 2.2.1 OVERVIEW 24 2.2.2 JITTER 26 2.2.3 CDR JITTER CHARACTERISTICS 33 2.3 CDR ARCHITECTURES 39 2.3.1 PLL-BASED CDR – WITH EXTERNAL REFERENCE CLOCK 39 2.3.2 DLL/PI-BASED CDR 44 2.3.3 PLL-BASED CDR – WITHOUT EXTERNAL REFERENCE CLOCK 47 2.4 FREQUENCY ACQUISITION SCHEME 50 2.4.1 TYPICAL FREQUENCY DETECTORS 50 2.4.1.1 DIGITAL QUADRICORRELATOR FREQUENCY DETECTOR 50 2.4.1.2 ROTATIONAL FREQUENCY DETECTOR 54 2.4.2 PRIOR WORKS 56 CHAPTER 3 DESIGN OF THE REFERENCELESS CDR USING SFD 58 3.1 OVERVIEW 58 3.2 PROPOSED FREQUENCY DETECTOR 62 3.2.1 MOTIVATION 62 3.2.2 PATTERN HISTOGRAM ANALYSIS 68 3.2.3 INTRODUCTION OF AUTOCOVARIANCE TO STOCHASTIC FREQUENCY DETECTOR 75 3.3 CIRCUIT IMPLEMENTATION 83 3.3.1 IMPLEMENTATION OF THE PROPOSED REFERENCELESS CDR 83 3.3.2 CONTINUOUS-TIME LINEAR EQUALIZER (CTLE) 85 3.3.3 DIGITALLY-CONTROLLED OSCILLATOR (DCO) 87 3.4 MEASUREMENT RESULTS 89 CHAPTER 4 CONCLUSION 99 APPENDIX A DETAILED FREQUENCY ACQUISITION WAVEFORMS OF THE PROPOSED SFD 100 BIBLIOGRAPHY 108 초 록 122박

Novel Systematic Phase Noise Reduction Techniques for Phase Interpolator Clock and Data Recovery

This work focused on high-speed source-synchronous clock and multi-channel data receivers for inter-chip communications. Designs of inter-chip communication are becoming increasingly difficult with the rise in clock rates and the reduction in voltage supplies. Data transmissions at rates of gigabits per second require a fast and accurate clock and data recovery system on the front end of receivers. Many designs allow for source-synchronous clocking architectures, but this work focused on a dual-loop with a phase-locked loop for frequency tracking and phase integrators for tracking each individual data lane. Limitations with the phase interpolator architecture cause systematic jitter, reducing the data eye. Various techniques exist that aim to reduce or eliminate this systematic jitter from phase interpolator architectures. A technique based on digital lock detection was developed for this work that eliminates the phase interpolator systematic jitter

A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit

Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050 mm(2) and consumes only 46 mW at 25 Gb/s. This is the smallest area and the lowest power consumption compared with the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic, and supports a wide operating range (12.5-25 Gb/s), which is a significantly larger range compared with the previous work. Finally, thanks to our digital architecture, the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with the most prior work, making our design truly adaptive

Techniques for low jitter clock multiplication

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 115-121).Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to path mismatch in the detector as well as analog nonidealities in the tuning circuits. This thesis proposes a mostly-digital tuning technique that drastically reduces deterministic jitter in phase realigning clock multipliers. The proposed technique eliminates path mismatch by using a single-path digital detection method that leverages a scrambling time-to-digital converter (TDC) and correlated double sampling to infer the tuning error from the difference in cycle periods of the output. By using a digital loop filter that consists of a digital accumulator, the tuning technique avoids the analog nonidealities of typical tuning paths. The scrambling TDC is not a contribution of this thesis. A highly-digital MDLL prototype that uses the proposed tuning technique consists of two custom 0.13 [mu]m ICs, an FPGA board, a discrete digital-to-analog converter (DAC) with effective 8 bits, and a simple RC filter. The measured performance (for a 1.6 GHz output and 50 MHz reference) demonstrated an overall jitter of 0.93 ps rms, and estimated random and deterministic jitter of 0.68 ps rms and 0.76 ps peak-to-peak, respectively. The proposed MDLL architecture is especially suitable for digital ICs, since its highly-digital architecture is mostly compatible with digital design flows, which eases its porting between technologies.by Belal Moheedin Helal.Ph.D