A Survey of Clock Synchronization Over Packet-Switched Networks

Clock synchronization is a prerequisite for the realization of emerging applications in various domains such as industrial automation and the intelligent power grid. This paper surveys the standardized protocols and technologies for providing synchronization of devices connected by packet-switched networks. A review of synchronization impairments and the state-of-the-art mechanisms to improve the synchronization accuracy is then presented. Providing microsecond to sub-microsecond synchronization accuracy under the presence of asymmetric delays in a cost-effective manner is a challenging problem, and still an open issue in many application scenarios. Further, security is of significant importance for systems where timing is critical. The security threats and solutions to protect exchanged synchronization messages are also discussed

Precise Network Time Monitoring: Picosecond-level packet timestamping for Fintech networks

Network visibility and monitoring are critical in modern networks due to the increased density, additional complexity, higher bandwidth, and lower latency requirements. Precise packet timestamping and synchronization are essential to temporally correlate captured information in different datacenter locations. This is key for visibility, event ordering and latency measurements in segments as telecom, power grids and electronic trading in finance, where order execution and reduced latency are critical for successful business outcomes. This contribution presents Precise Network Time Monitoring (PNTM), a novel mechanism for asynchronous Ethernet packet timestamping which adapts a Digital Dual Mixer Time Difference (DDMTD) implemented in an FPGA. Picosecond-precision packet timestamping is outlined for 1 Gigabit Ethernet. Furthermore, this approach is combined with the White Rabbit (WR) synchronization protocol, used as reference for the IEEE 1588-2019 High Accuracy Profile to provide unprecedented packet capturing correlation accuracy in distributed network scenarios thanks to its sub-nanosecond time transfer. The paper presents different application examples, describes the method of implementation, integration of WR with PNTM and subsequently describes experiments to demonstrate that PNTM is a suitable picosecond-level distributed packet timestamping solutionNational project AMIGA7 RTI2018-096228-B-C32Andalusian project SINPA B-TIC-445-UGR1

Evaluation of IEEE 802.1 Time Sensitive Networking Performance for Microgrid and Smart Grid Power System Applications

Proliferation of distributed energy resources and the importance of smart energy management has led to increased interest in microgrids. A microgrid is an area of the grid that can be disconnected and operated independently from the main grid when required and can generate some or all of its own energy needs with distributed energy resources and battery storage. This allows for the microgrid area to continue operating even when the main grid is unavailable. In addition, often a microgrid can utilize waste heat from energy generation to drive thermal loads, further improving energy utilization. This leads to increased reliability and overall efficiency in the microgrid area.As microgrids (and by extension the smart grid) become more widespread, new methods of communication and control are required to aid in management of many different distributed entities. One such communication architecture that may prove useful is the set of IEEE 802.1 Time Sensitive Networking (TSN) standards. These standards specify improvements and new capabilities for LAN based communication networks that previously made them unsuitable for widespread deployment in a power system setting. These standards include specifications for low latency guarantees, clock synchronization, data frame redundancy, and centralized system administration. These capabilities were previously available on proprietary or application specific solutions. However, they will now be available as part of the Ethernet standard, enabling backwards compatibility with existing network architecture and support with future advances.Two of the featured standards, IEEE 802.1AS (governing time-synchronization) and IEEE 802.1Qbv (governing time aware traffic shaping), will be tested and evaluated for their potential utility in power systems and microgrid applications. These tests will measure the latency achievable using TSN over a network at various levels of congestion and compare these results with UDP and TCP protocols. In addition, the ability to use synchronized clocks to generate waveforms for microgrid inverter synchronization will be explored

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Desynchronization: Synthesis of asynchronous circuits from synchronous specifications

Asynchronous implementation techniques, which measure logic delays at run time and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst-case delays at design time, and constrain the clock cycle accordingly. De-synchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus permitting widespread adoption of asynchronicity, without requiring special design skills or tools. In this paper, we first of all study different protocols for de-synchronization and formally prove their correctness, using techniques originally developed for distributed deployment of synchronous language specifications. We also provide a taxonomy of existing protocols for asynchronous latch controllers, covering in particular the four-phase handshake protocols devised in the literature for micro-pipelines. We then propose a new controller which exhibits provably maximal concurrency, and analyze the performance of desynchronized circuits with respect to the original synchronous optimized implementation. We finally prove the feasibility and effectiveness of our approach, by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architectur

Multi-sample differential protection scheme in DC microgrids

This paper proposes a novel solution to the issue of protection instability caused by time synchronization error in high-speed differential protection schemes for DC microgrids. DC microgrids provide a more efficient platform to integrate fast-growing renewable energy sources, energy storage systems, and electronic loads. However, the integration of distributed generators (DG) may result in variable fault current magnitude and direction during fault conditions, potentially causing mis-coordination of conventional time graded overcurrent relays. One identified solution to this issue utilizes high-speed differential protection schemes to maintain effective selectivity in DG-dominated DC microgrids. However, as DC short-circuit fault currents are highly transient, microseconds of synchronization error in the measured line currents may cause protection stability issues, whereby mal-operation of relays may occur as a result of faults external to the protected zone. This paper investigates the impact of time synchronization errors for high-speed differential protection in DC distribution systems. It then proposes a multi-sample differential (MSD) scheme that performs multiple differential comparisons over a sampling window to ensure the stability of high-speed differential protection schemes for external faults whilst maintaining sensitivity to internal faults

Secure GPS clock synchronization in smart grids

Tese de mestrado, Segurança Informática, Universidade de Lisboa, Faculdade de Ciências, 2015As smart grids resultaram da integração da rede elétrica atual no mundo digital. Isso traz várias vantagens às redes elétricas, como uma instalação, configuração e manutenção mais simples e eficiente, mas também a fácil integração na rede de novas tecnologias. Enquanto as redes elétricas continuam a crescer em dimensão e complexidade, elas tornam-se mais importantes para a sociedade e subsequentemente mais sujeitas a ataques distintos. Alguns dos objetivos mais importantes da smart grid são: acomodar uma grande variedade de tecnologias de produção de eletricidade como a eólica, solar e geotérmica; ser resiliente a ataques físicos e ciber-ataques; ter mecanismos de deteção, análise e resposta automática a incidentes; dar mais poder ao consumidor final sobre como e quando a energia pode ser comprada ou consumida. Para implementar actividades relacionadas com a monitorização do estado da smart grid, vários componentes especializados são geograficamente distribuídos pela rede. Um dos dispositivos críticos é o Phase Measurement Unit (Unidade de Medição de Fase) (PMU). Este dispositivo é usado para estimar o estado da smart grid num determinado momento, recolhendo várias métricas sobre a qualidade do sinal elétrico. Para se conseguir criar uma imagem geral da rede inteira, todos estes dispositivos necessitam de ser sincronizados no tempo, assegurando assim que as medições são efetuadas aproximadamente no mesmo instante. A sincronização do tempo desempenha um papel crucial na estabilidade e no funcionamento correto de todos os componentes da smart grid. Dada a importância da sincronização de tempo, e a falta de qualquer tipo de proteção nas soluções atuais, este sistema torna-se num alvo potencial para atacantes. Em conformidade com os standards, a precisão dos relógios dos PMU’s devem ter um erro máximo na ordem dos 30 µs. Isso garante que a informação recolhida sobre o estado da smart grid é válida. Hoje em dia este requisito é satisfeito usando equipamentos GPS em cada sítio onde se encontra um PMU. Quando o GPS foi concebido, não se pensou que podia vir a ter o sucesso e o impacto atual e, portanto, assegurar a sua segurança não foi um ponto importante. Ao longo do tempo passou a ser usado em infraestruturas críticas, o que introduz eventuais problemas graves de segurança. As smart grids são uma destas estruturas críticas onde o GPS está a ser usado sem qualquer tipo de proteção. Atualmente existe também uma versão segura do GPS que é empregue pelas forças militares. Os dispositivos que conseguem decifrar este sinal só estão disponíveis ao exército. Por além disso, todos os detalhes sobre o funcionamento do algoritmo de cifra são mantidos em segredo. Ao longo dos anos foram desenvolvidos vários tipos de ataques ao GPS. O mais básico é o Blocking que consiste simplesmente em impedir a comunicação entre a antena do recetor e o sinal GPS. Isso pode ser conseguido de uma maneira tão simples como tapar a antena com um bocado de metal. Um ataque que tenta também quebrar a ligação com o satélite é o Jamming. A ideia deste ataque é introduzir ruído suficiente para que o recetor não consiga distinguir o sinal original. Estes dois tipos de ataques só conseguem perturbar o funcionamento do recetor GPS. Um tipo de ataque mais potente é o Spoofing. Este ataque consegue modificar o sinal original vindo do satélite de forma a enganar o recetor. Assim é possível fazer com que o recetor GPS mostre uma posição¸ ou tempo incorretos. Nesta dissertação também foi analisada uma evolução deste ataque que tem como alvo a alteração ilegítima dos dados contidos no sinal. Isso pode fazer como que o recetor falhe ou deixe de poder ser usado. Os algoritmos de sincronização de relógios existentes hoje em dia, nomeadamente o Network Time Protocol (NTP) e o Precision Time Protocol (PTP), não são suficientemente robustos, em termos de segurança ou precisão, para serem utilizados na smart grid. O NTP foi concebido para a sincronização de relógios em redes de grande escala mas não consegue fornecer a precisão necessária para os requisitos da smart grid. Por outro lado temos o PTP que consegue atingir uma precisão na ordem dos nanosegundos em certas condições, mas é muito sensível a atrasos e oscilações na rede. Isso faz com que o PTP só consiga garantir uma precisão de tempo na ordem dos nanosegundos em redes de pequena escala. A smart grid usa uma rede de alta velocidade com relativamente pouco tráfego, o que torna o PTP uma possível solução para algumas partes dessa rede. Em termos de segurançaa, o PTP não está preparado para ser utilizado num ambiente tão crítico como a smart grid, sendo suscetível a ataques. O foco desta investigação é encontrar um algoritmo resiliente a faltas, capaz de satisfazer os requisitos de sincronização de tempo necessários para o correto funcionamento da smart grid. Foi desenvolvida uma solução baseada no PTP, que consegue cumprir os requisitos de precisão temporal na smart grid e também consegue mitigar todos os tipos de ataques ao GPS que foram identificados. Para além disso, a solução também permite reduzir o número de recetores de GPS necessários para o funcionamento correto da smart grid.Smart grids resulted from the integration of computer technologies into the current power grid. This brings several advantages, allowing for a faster and more efficient deployment, configuration and maintenance, as well as easy integration of new energy sources (e.g., wind and solar). As smart grids continue to grow in size and complexity, they become subject to failures and attacks from different sources. Time synchronization plays a crucial role in the stability and correct functioning of many grid components. Considering how sensitive time synchronization is, the tight restrictions imposed for correct operation and the lack of any kind of protection, makes this service a potential prime target for attackers. Today most of the time synchronization requirements are met using relatively expensive GPS hardware placed in some locations of the smart grid. When GPS was first devised, nobody could have predicted the success and the impact that it would have and therefore, security was never an important concern. Through the years, it slowly gained entrance into more critical systems, where it was never intended to be used, which can lead to serious security problems. The smart grid is just one of these critical systems where GPS is being employed without any kind of protection. The focus of this research is trying to solve this problem, by proposing a more secure and robust clock synchronization algorithm. A solution based on the Precision Time Protocol (PTP) was developed that manages to fulfill the time synchronization requirements of the smart grid and is also capable of mitigating all types of identified GPS attacks. As an added benefit, the solution may also reduce the number of GPS receivers necessary for the correct operation of the smart grid, contributing to decrease costs

Characterization of real-time computers

A real-time system consists of a computer controller and controlled processes. Despite the synergistic relationship between these two components, they have been traditionally designed and analyzed independently of and separately from each other; namely, computer controllers by computer scientists/engineers and controlled processes by control scientists. As a remedy for this problem, in this report real-time computers are characterized by performance measures based on computer controller response time that are: (1) congruent to the real-time applications, (2) able to offer an objective comparison of rival computer systems, and (3) experimentally measurable/determinable. These measures, unlike others, provide the real-time computer controller with a natural link to controlled processes. In order to demonstrate their utility and power, these measures are first determined for example controlled processes on the basis of control performance functionals. They are then used for two important real-time multiprocessor design applications - the number-power tradeoff and fault-masking and synchronization