Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Two- and Three-dimensional High Performance, Patterned Overlay Multi-chip Module Technology

A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage

Integrated capacitors for conductive lithographic film circuits

This paper reports on fabrication of low-value embedded capacitors in conductive lithographic film (CLF) circuit boards. The CLF process is a low-cost and high speed manufacturing technique for flexible circuits and systems. We report on the construction and electrical characteristics of CLF capacitor structures printed onto flexible substrates. These components comprise a single polyester dielectric layer, which separates the printed electrode films. Multilayer circuit boards with printed components and interconnect can be fabricated using this technique

Additively Manufactured RF Components, Packaging, Modules, and Flexible Modular Phased Arrays Enabling Widespread Massively Scalable mmWave/5G Applications

The 5G era is here and with it comes many challenges, particularily facing the high frequency mmWave adoption. This is because of the cost to implement such dense networks is much greater due to the high propagation losses of signals that range from 26 GHz to 40 GHz. Therefore there needs to be a way to utilize a method of fabrication that can change with the various environments that 5G will be deployed in, be it dense urban areas or suburban sprawl. In this research, the focus is on making these RF components utilized for 5G at low cost and modular with a focus on additive manufacturing. Since additive manufacturing is a rapid prototyping technique, the technology can be quickly adjusted and altered to meet certain specifications with negligible overhead. Several areas of research will be explored. Firstly, various RF passive components such as additively manufactured antennas and couplers with a combination hybrid inkjet and 3D printing will be discussed. Passive components are critical for evaluating the process of additive manufacturing for high frequency operation. Secondly, various structures will be evaluated specifically for packaging mmWave ICs, including interconnects, smart packaging and encapsulants for use in single or multichip modules. Thirdly, various antenna fabrication techniques will be explored which enables fully integrated ICs with antennas, called System on Antenna (SoA) which utilizes both inkjet and 3D printing to combine antennas and ICs into modules. These modules, can then be built into arrays in a modular fashion, allowing for large or smaller arrays to be assembled on the fly. Finally, a method of calibrating the arrays is introduced, utilizing inkjet printed sensors. This allows the sensor to actively detect bends and deformations in the array and restore optimal antenna array performance. Built for flexible phased arrays, the sensor is designed for implementation for ubiquitous use, meaning that its can be placed on any surface, which enables widespread use of 5G technologies.Ph.D

Multi-chip module interconnections at microwave frequencies: electromagnetic simulation and material characterisation

In this work both the interconnections and materials used in multi-chip modules (MCMs) at microwave frequencies have been investigated. The electrical behaviour of the interconnections was studied using commercially available 2.SD and 3D electromagnetic simulators (HFSSTM, MDSTM and Momentum™). State-of-the-art conductive and dielectric film materials used in the fabrication of multi-layer MCM structures were characterized using microstrip/wave guide resonator techniques. The models chosen for simulation of interconnections are commensurate with those in current use in MCM technology. Crosstalk between microstrip conductors in multi-layer MCM structures was simulated and new knowledge leading to new design rules was obtained.Typical elements in MCM interconnect structures, such as vias, bends and airbridges were also investigated. The principal features of these elements were simulated and the results were obtained in S-parameter form. Based on the simulated results, these parasitic elements were modelled in terms of their equivalent circuits which can be used in circuit simulators to aid more rigorous MCM circuit design. A microstrip ring resonator, fabricated using the newly developed conductive material from Heraeus, was employed to measure the line loss. New techniques have been developed to measure the permittivity and loss tangent of thin dielectric films. In the previous methods for the measurement of these films, the accuracy in measuring the relative permittivity is limited and there is no available technique to measure the loss tangent. A novel cavity perturbation method was developed to accurately measure both the relative permittivity and loss tangent of the films deposited on a supporting substrate. An additional independent technique, derived from transmission line theory, for measuring the relative permittivity of dielectric film was also established. A particular feature of the new teclmiques, which led to high accuracy in measuring dielectric constant and loss tangent was the positioning of the dielectric film in the region of maximum electric field strength, thereby ensuring maximum interaction between the electric field and the film material. A rigorous error analysis was performed on the new techniques, which led to the establishment of practical measurement correction factors. A simple and rigorous method has also been developed to accurately measure the loss tangent of dielectrics with known dielectric constant using a resonant cavity. The novel method eliminates the need for any physical measurement of the dielectric sample. The new technique should permit the development of techniques for very high frequency characterisation of dielectric materials

Development and Packaging of Microsystems Using Foundry Services

Micro-electro-mechanical systems (MEMS) are a new and rapidly growing field of research. Several advances to the MEMS state of the art were achieved through design and characterization of novel devices. Empirical and theoretical model of polysilicon thermal actuators were developed to understand their behavior. The most extensive investigation of the Multi-User MEMS Processes (MUMPs) polysilicon resistivity was also performed. The first published value for the thermal coefficient of resistivity (TCR) of the MUMPs Poly 1 layer was determined as 1.25 x 10(exp -3)/K. The sheet resistance of the MUMPs polysilicon layers was found to be dependent on linewidth due to presence or absence of lateral phosphorus diffusion. The functional integration of MEMS with CMOS was demonstrated through the design of automated positioning and assembly systems, and a new power averaging scheme was devised. Packaging of MEMS using foundry multichip modules (MCMs) was shown to be a feasible approach to physical integration of MEMS with microelectronics. MEMS test die were packaged using Micro Module Systems MCM-D and General Electric High Density Intercounect and Chip-on-Flex MCM foundries. Xenon difluoride (XeF2) was found to be an excellent post-packaging etchant for bulk micromachined MEMS. For surface micromachining, hydrofluoric acid (HF) can be used

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Laser-assisted bumping for flip chip assembly

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