Polymorphic computing abstraction for heterogeneous architectures

Integration of multiple computing paradigms onto system on chip (SoC) has pushed the boundaries of design space exploration for hardware architectures and computing system software stack. The heterogeneity of computing styles in SoC has created a new class of architectures referred to as Heterogeneous Architectures. Novel applications developed to exploit the different computing styles are user centric for embedded SoC. Software and hardware designers are faced with several challenges to harness the full potential of heterogeneous architectures. Applications have to execute on more than one compute style to increase overall SoC resource utilization. The implication of such an abstraction is that application threads need to be polymorphic. Operating system layer is thus faced with the problem of scheduling polymorphic threads. Resource allocation is also an important problem to be dealt by the OS. Morphism evolution of application threads is constrained by the availability of heterogeneous computing resources. Traditional design optimization goals such as computational power and lower energy per computation are inadequate to satisfy user centric application resource needs. Resource allocation decisions at application layer need to permeate to the architectural layer to avoid conflicting demands which may affect energy-delay characteristics of application threads. We propose Polymorphic computing abstraction as a unified computing model for heterogeneous architectures to address the above issues. Simulation environment for polymorphic applications is developed and evaluated under various scheduling strategies to determine the effectiveness of polymorphism abstraction on resource allocation. User satisfaction model is also developed to complement polymorphism and used for optimization of resource utilization at application and network layer of embedded systems

Run-time management for future MPSoC platforms

In recent years, we are witnessing the dawning of the Multi-Processor Systemon- Chip (MPSoC) era. In essence, this era is triggered by the need to handle more complex applications, while reducing overall cost of embedded (handheld) devices. This cost will mainly be determined by the cost of the hardware platform and the cost of designing applications for that platform. The cost of a hardware platform will partly depend on its production volume. In turn, this means that ??exible, (easily) programmable multi-purpose platforms will exhibit a lower cost. A multi-purpose platform not only requires ??exibility, but should also combine a high performance with a low power consumption. To this end, MPSoC devices integrate computer architectural properties of various computing domains. Just like large-scale parallel and distributed systems, they contain multiple heterogeneous processing elements interconnected by a scalable, network-like structure. This helps in achieving scalable high performance. As in most mobile or portable embedded systems, there is a need for low-power operation and real-time behavior. The cost of designing applications is equally important. Indeed, the actual value of future MPSoC devices is not contained within the embedded multiprocessor IC, but in their capability to provide the user of the device with an amount of services or experiences. So from an application viewpoint, MPSoCs are designed to ef??ciently process multimedia content in applications like video players, video conferencing, 3D gaming, augmented reality, etc. Such applications typically require a lot of processing power and a signi??cant amount of memory. To keep up with ever evolving user needs and with new application standards appearing at a fast pace, MPSoC platforms need to be be easily programmable. Application scalability, i.e. the ability to use just enough platform resources according to the user requirements and with respect to the device capabilities is also an important factor. Hence scalability, ??exibility, real-time behavior, a high performance, a low power consumption and, ??nally, programmability are key components in realizing the success of MPSoC platforms. The run-time manager is logically located between the application layer en the platform layer. It has a crucial role in realizing these MPSoC requirements. As it abstracts the platform hardware, it improves platform programmability. By deciding on resource assignment at run-time and based on the performance requirements of the user, the needs of the application and the capabilities of the platform, it contributes to ??exibility, scalability and to low power operation. As it has an arbiter function between different applications, it enables real-time behavior. This thesis details the key components of such an MPSoC run-time manager and provides a proof-of-concept implementation. These key components include application quality management algorithms linked to MPSoC resource management mechanisms and policies, adapted to the provided MPSoC platform services. First, we describe the role, the responsibilities and the boundary conditions of an MPSoC run-time manager in a generic way. This includes a de??nition of the multiprocessor run-time management design space, a description of the run-time manager design trade-offs and a brief discussion on how these trade-offs affect the key MPSoC requirements. This design space de??nition and the trade-offs are illustrated based on ongoing research and on existing commercial and academic multiprocessor run-time management solutions. Consequently, we introduce a fast and ef??cient resource allocation heuristic that considers FPGA fabric properties such as fragmentation. In addition, this thesis introduces a novel task assignment algorithm for handling soft IP cores denoted as hierarchical con??guration. Hierarchical con??guration managed by the run-time manager enables easier application design and increases the run-time spatial mapping freedom. In turn, this improves the performance of the resource assignment algorithm. Furthermore, we introduce run-time task migration components. We detail a new run-time task migration policy closely coupled to the run-time resource assignment algorithm. In addition to detailing a design-environment supported mechanism that enables moving tasks between an ISP and ??ne-grained recon??gurable hardware, we also propose two novel task migration mechanisms tailored to the Network-on-Chip environment. Finally, we propose a novel mechanism for task migration initiation, based on reusing debug registers in modern embedded microprocessors. We propose a reactive on-chip communication management mechanism. We show that by exploiting an injection rate control mechanism it is possible to provide a communication management system capable of providing a soft (reactive) QoS in a NoC. We introduce a novel, platform independent run-time algorithm to perform quality management, i.e. to select an application quality operating point at run-time based on the user requirements and the available platform resources, as reported by the resource manager. This contribution also proposes a novel way to manage the interaction between the quality manager and the resource manager. In order to have a the realistic, reproducible and ??exible run-time manager testbench with respect to applications with multiple quality levels and implementation tradev offs, we have created an input data generation tool denoted Pareto Surfaces For Free (PSFF). The the PSFF tool is, to the best of our knowledge, the ??rst tool that generates multiple realistic application operating points either based on pro??ling information of a real-life application or based on a designer-controlled random generator. Finally, we provide a proof-of-concept demonstrator that combines these concepts and shows how these mechanisms and policies can operate for real-life situations. In addition, we show that the proposed solutions can be integrated into existing platform operating systems

Energy Harvesting-Aware Design for Wireless Nanonetworks

Nanotechnology advancement promises to enable a new era of computing and communication devices by shifting micro scale chip design to nano scale chip design. Nanonetworks are envisioned as artifacts of nanotechnology in the domain of networking and communication. These networks will consist of nodes of nanometer to micrometer in size, with a communication range up to 1 meter. These nodes could be used in various biomedical, industrial, and environmental monitoring applications, where a nanoscale level of sensing, monitoring, control and communication is required. The special characteristics of nanonetworks require the revisiting of network design. More specifically, nanoscale limitations, new paradigms of THz communication, and power supply via energy harvesting are the main issues that are not included in traditional network design methods. In this regard, this dissertation investigates and develops some solutions in the realization of nanonetworks. Particularly, the following major solutions are investigated. (I) The energy harvesting and energy consumption processes are modeled and evaluated simultaneously. This model includes the stochastic nature of energy arrival as well as the pulse-based communication model for energy consumption. The model identifies the effect of various parameters in this joint process. (II) Next, an optimization problem is developed to find the best combination of these parameters. Specifically, optimum values for packet size, code weight, and repetition are found in order to minimize the energy consumption while satisfying some application requirements (i.e., delay and reliability). (III) An optimum policy for energy consumption to achieve the maximum utilization of harvested energy is developed. The goal of this scheme is to take advantage of available harvested energy as much as possible while satisfying defined performance metrics. (IV) A communication scheme that tries to maximize the data throughput via a distributed and scalable coordination while avoiding the collision among neighbors is the last problem to be investigated. The goal is to design an energy harvesting-aware and distributed mechanism that could coordinate data transmission among neighbors. (V) Finally, all these solutions are combined together to create a data link layer model for nanonodes. We believe resolving these issues could be the first step towards an energy harvesting-aware network design for wireless nanosensor networks

Design Space Exploration and Resource Management of Multi/Many-Core Systems

The increasing demand of processing a higher number of applications and related data on computing platforms has resulted in reliance on multi-/many-core chips as they facilitate parallel processing. However, there is a desire for these platforms to be energy-efficient and reliable, and they need to perform secure computations for the interest of the whole community. This book provides perspectives on the aforementioned aspects from leading researchers in terms of state-of-the-art contributions and upcoming trends

Segment Routing: a Comprehensive Survey of Research Activities, Standardization Efforts and Implementation Results

Fixed and mobile telecom operators, enterprise network operators and cloud providers strive to face the challenging demands coming from the evolution of IP networks (e.g. huge bandwidth requirements, integration of billions of devices and millions of services in the cloud). Proposed in the early 2010s, Segment Routing (SR) architecture helps face these challenging demands, and it is currently being adopted and deployed. SR architecture is based on the concept of source routing and has interesting scalability properties, as it dramatically reduces the amount of state information to be configured in the core nodes to support complex services. SR architecture was first implemented with the MPLS dataplane and then, quite recently, with the IPv6 dataplane (SRv6). IPv6 SR architecture (SRv6) has been extended from the simple steering of packets across nodes to a general network programming approach, making it very suitable for use cases such as Service Function Chaining and Network Function Virtualization. In this paper we present a tutorial and a comprehensive survey on SR technology, analyzing standardization efforts, patents, research activities and implementation results. We start with an introduction on the motivations for Segment Routing and an overview of its evolution and standardization. Then, we provide a tutorial on Segment Routing technology, with a focus on the novel SRv6 solution. We discuss the standardization efforts and the patents providing details on the most important documents and mentioning other ongoing activities. We then thoroughly analyze research activities according to a taxonomy. We have identified 8 main categories during our analysis of the current state of play: Monitoring, Traffic Engineering, Failure Recovery, Centrally Controlled Architectures, Path Encoding, Network Programming, Performance Evaluation and Miscellaneous...Comment: SUBMITTED TO IEEE COMMUNICATIONS SURVEYS & TUTORIAL

Intelligent Circuits and Systems

ICICS-2020 is the third conference initiated by the School of Electronics and Electrical Engineering at Lovely Professional University that explored recent innovations of researchers working for the development of smart and green technologies in the fields of Energy, Electronics, Communications, Computers, and Control. ICICS provides innovators to identify new opportunities for the social and economic benefits of society.　 This conference bridges the gap between academics and R&D institutions, social visionaries, and experts from all strata of society to present their ongoing research activities and foster research relations between them. It provides opportunities for the exchange of new ideas, applications, and experiences in the field of smart technologies and finding global partners for future collaboration. The ICICS-2020 was conducted in two broad categories, Intelligent Circuits & Intelligent Systems and Emerging Technologies in Electrical Engineering

Characterization, design and re-optimization on multi-layer optical networks

L'augment de volum de tràfic IP provocat per l'increment de serveis multimèdia com HDTV o vídeo conferència planteja nous reptes als operadors de xarxa per tal de proveir transmissió de dades eficient. Tot i que les xarxes mallades amb multiplexació per divisió de longitud d'ona (DWDM) suporten connexions òptiques de gran velocitat, aquestes xarxes manquen de flexibilitat per suportar tràfic d’inferior granularitat, fet que provoca un pobre ús d'ample de banda. Per fer front al transport d'aquest tràfic heterogeni, les xarxes multicapa representen la millor solució. Les xarxes òptiques multicapa permeten optimitzar la capacitat mitjançant l'empaquetament de connexions de baixa velocitat dins de connexions òptiques de gran velocitat. Durant aquesta operació, es crea i modifica constantment una topologia virtual dinàmica gràcies al pla de control responsable d’aquestes operacions. Donada aquesta dinamicitat, un ús sub-òptim de recursos pot existir a la xarxa en un moment donat. En aquest context, una re-optimizació periòdica dels recursos utilitzats pot ser aplicada, millorant així l'ús de recursos. Aquesta tesi està dedicada a la caracterització, planificació, i re-optimització de xarxes òptiques multicapa de nova generació des d’un punt de vista unificat incloent optimització als nivells de capa física, capa òptica, capa virtual i pla de control. Concretament s'han desenvolupat models estadístics i de programació matemàtica i meta-heurístiques. Aquest objectiu principal s'ha assolit mitjançant cinc objectius concrets cobrint diversos temes oberts de recerca. En primer lloc, proposem una metodologia estadística per millorar el càlcul del factor Q en problemes d'assignació de ruta i longitud d'ona considerant interaccions físiques (IA-RWA). Amb aquest objectiu, proposem dos models estadístics per computar l'efecte XPM (el coll d'ampolla en termes de computació i complexitat) per problemes IA-RWA, demostrant la precisió d’ambdós models en el càlcul del factor Q en escenaris reals de tràfic. En segon lloc i fixant-nos a la capa òptica, presentem un nou particionament del conjunt de longituds d'ona que permet maximitzar, respecte el cas habitual, la quantitat de tràfic extra proveït en entorns de protecció compartida. Concretament, definim diversos models estadístics per estimar la quantitat de tràfic donat un grau de servei objectiu, i diferents models de planificació de xarxa amb l'objectiu de maximitzar els ingressos previstos i el valor actual net de la xarxa. Després de resoldre aquests problemes per xarxes reals, concloem que la nostra proposta maximitza ambdós objectius. En tercer lloc, afrontem el disseny de xarxes multicapa robustes davant de fallida simple a la capa IP/MPLS i als enllaços de fibra. Per resoldre aquest problema eficientment, proposem un enfocament basat en sobre-dimensionar l'equipament de la capa IP/MPLS i recuperar la connectivitat i el comparem amb la solució convencional basada en duplicar la capa IP/MPLS. Després de comparar solucions mitjançant models ILP i heurístiques, concloem que la nostra solució permet obtenir un estalvi significatiu en termes de costos de desplegament. Com a quart objectiu, introduïm un mecanisme adaptatiu per reduir l'ús de ports opto-electrònics (O/E) en xarxes multicapa sota escenaris de tràfic dinàmic. Una formulació ILP i diverses heurístiques són desenvolupades per resoldre aquest problema, que permet reduir significativament l’ús de ports O/E en temps molt curts. Finalment, adrecem el problema de disseny resilient del pla de control GMPLS. Després de proposar un nou model analític per quantificar la resiliència en topologies mallades de pla de control, usem aquest model per proposar un problema de disseny de pla de control. Proposem un procediment iteratiu lineal i una heurística i els usem per resoldre instàncies reals, arribant a la conclusió que es pot reduir significativament la quantitat d'enllaços del pla de control sense afectar la qualitat de servei a la xarxa.The explosion of IP traffic due to the increase of IP-based multimedia services such as HDTV or video conferencing poses new challenges to network operators to provide a cost-effective data transmission. Although Dense Wavelength Division Multiplexing (DWDM) meshed transport networks support high-speed optical connections, these networks lack the flexibility to support sub-wavelength traffic leading to poor bandwidth usage. To cope with the transport of that huge and heterogeneous amount of traffic, multilayer networks represent the most accepted architectural solution. Multilayer optical networks allow optimizing network capacity by means of packing several low-speed traffic streams into higher-speed optical connections (lightpaths). During this operation, a dynamic virtual topology is created and modified the whole time thanks to a control plane responsible for the establishment, maintenance, and release of connections. Because of this dynamicity, a suboptimal allocation of resources may exist at any time. In this context, a periodically resource reallocation could be deployed in the network, thus improving network resource utilization. This thesis is devoted to the characterization, planning, and re-optimization of next-generation multilayer networks from an integral perspective including physical layer, optical layer, virtual layer, and control plane optimization. To this aim, statistical models, mathematical programming models and meta-heuristics are developed. More specifically, this main objective has been attained by developing five goals covering different open issues. First, we provide a statistical methodology to improve the computation of the Q-factor for impairment-aware routing and wavelength assignment problems (IA-RWA). To this aim we propose two statistical models to compute the Cross-Phase Modulation variance (which represents the bottleneck in terms of computation time and complexity) in off-line and on-line IA-RWA problems, proving the accuracy of both models when computing Q-factor values in real traffic scenarios. Second and moving to the optical layer, we present a new wavelength partitioning scheme that allows maximizing the amount of extra traffic provided in shared path protected environments compared with current solutions. Specifically, we define several statistical models to estimate the traffic intensity given a target grade of service, and different network planning problems for maximizing the expected revenues and net present value. After solving these problems for real networks, we conclude that our proposed scheme maximizes both revenues and NPV. Third, we tackle the design of survivable multilayer networks against single failures at the IP/MPLS layer and WSON links. To efficiently solve this problem, we propose a new approach based on over-dimensioning IP/MPLS devices and lightpath connectivity and recovery and we compare it against the conventional solution based on duplicating backbone IP/MPLS nodes. After evaluating both approaches by means of ILP models and heuristic algorithms, we conclude that our proposed approach leads to significant CAPEX savings. Fourth, we introduce an adaptive mechanism to reduce the usage of opto-electronic (O/E) ports of IP/MPLS-over-WSON multilayer networks in dynamic scenarios. A ILP formulation and several heuristics are developed to solve this problem, which allows significantly reducing the usage of O/E ports in very short running times. Finally, we address the design of resilient control plane topologies in GMPLS-enabled transport networks. After proposing a novel analytical model to quantify the resilience in mesh control plane topologies, we use this model to propose a problem to design the control plane topology. An iterative model and a heuristic are proposed and used to solve real instances, concluding that a significant reduction in the number of control plane links can be performed without affecting the quality of service of the network

Flight testing of a remotely piloted vehicle for aircraft parameter estimation purposes

The contribution of this research effort was to show that a reliable RPV could be built, tested, and successfully used for flight testing and parameter estimation purposes, in an academic setting. This was a fundamental step towards the creation of an automated Unmanned Aerial Vehicle (UAV). This research project was divided into four phases. Phase one involved the construction, development, and initial flight of a Remotely Piloted Vehicle (RPV), the West Virginia University (WVU) Boeing 777 (B777) aircraft. This phase included the creation of an onboard instrumentation system to provide aircraft flight data. The objective of the second phase was to estimate the longitudinal and lateral-directional stability and control derivatives from actual flight data for the B777 model. This involved performing and recording flight test maneuvers used for analysis of the longitudinal and lateral-directional estimates. Flight maneuvers included control surface doublets produced by the elevator, aileron, and rudder controls. A parameter estimation program known as pEst, developed at NASA Dryden Flight Research Center (DFRC), was used to compute the off-line estimates of parameters from collected flight data. This estimation software uses the Maximum Likelihood (ML) method with a Newton-Raphson (NR) minimization algorithm. The mathematical model used a traditional static and dynamic derivative buildup. Phase three focused on comparing a linear model obtained from the phase two ML estimates, with linear models obtained from a (i) Batch Least Squares Technique (BLS) and (ii) a technique from the Matlab system identification toolbox. Historically, aircraft parameter estimation has been performed off-line using recorded flight data from specifically designed maneuvers. In recent years, several on-line parameter identification techniques have been evaluated for real-time on-line applications. Along this research line, a novel contribution of this work was to compare the off-line estimation results with results obtained using a recently introduced frequency based on-line estimation method. Specifically, phase four focused on comparing the ML results with a frequency domain based on-line estimation technique. The RPV vehicle and payload was designed and constructed with the combined efforts of WVU researchers, graduate and undergraduate students of the Mechanical and Aerospace Engineering Department, and a private sub-contractor, Craig Aviation

Energy Demand Response for High-Performance Computing Systems

The growing computational demand of scientific applications has greatly motivated the development of large-scale high-performance computing (HPC) systems in the past decade. To accommodate the increasing demand of applications, HPC systems have been going through dramatic architectural changes (e.g., introduction of many-core and multi-core systems, rapid growth of complex interconnection network for efficient communication between thousands of nodes), as well as significant increase in size (e.g., modern supercomputers consist of hundreds of thousands of nodes). With such changes in architecture and size, the energy consumption by these systems has increased significantly. With the advent of exascale supercomputers in the next few years, power consumption of the HPC systems will surely increase; some systems may even consume hundreds of megawatts of electricity. Demand response programs are designed to help the energy service providers to stabilize the power system by reducing the energy consumption of participating systems during the time periods of high demand power usage or temporary shortage in power supply. This dissertation focuses on developing energy-efficient demand-response models and algorithms to enable HPC system\u27s demand response participation. In the first part, we present interconnection network models for performance prediction of large-scale HPC applications. They are based on interconnected topologies widely used in HPC systems: dragonfly, torus, and fat-tree. Our interconnect models are fully integrated with an implementation of message-passing interface (MPI) that can mimic most of its functions with packet-level accuracy. Extensive experiments show that our integrated models provide good accuracy for predicting the network behavior, while at the same time allowing for good parallel scaling performance. In the second part, we present an energy-efficient demand-response model to reduce HPC systems\u27 energy consumption during demand response periods. We propose HPC job scheduling and resource provisioning schemes to enable HPC system\u27s emergency demand response participation. In the final part, we propose an economic demand-response model to allow both HPC operator and HPC users to jointly reduce HPC system\u27s energy cost. Our proposed model allows the participation of HPC systems in economic demand-response programs through a contract-based rewarding scheme that can incentivize HPC users to participate in demand response