Circuit solutions to compensate for device degradation in analog design in scaled technologies

The continued aggressive scaling of semiconductor devices has had detrimental effects on the performance of those devices as used in analog circuitry. Specifically, the maximum intrinsic gain (MIG) of the devices continues to degrade as the device channel lengths are reduced below 100 nm and beyond. MIG is shown to degrade from 21.6 dB in a 180 nm technology to 12.2 dB in a 65 nm technology despite the application of traditional design techniques including device size scaling and bias voltage increases. This reduction in MIG along with other process scaling effects significantly complicates the design of linear amplifiers in these technologies. This work proposes the use of positive feedback to compensate for MIG degradation in linear amplifier design in scaled technologies. Criteria for stable and process tolerant design are derived and examined in the context of amplifier models of varying degrees of complexity. This analysis defines an all-encompassing positive feedback design methodology for use in linear amplifier design of low-gain high-frequency amplifier design. Additionally, the effects of positive feedback are compared and contrasted to the effects of the commonly studied negative feedback design methodology. Finally, the methodology is applied to a differential amplifier stage in TSMC\u27s 65 nm process using standard threshold voltage, thin oxide CMOS devices. These amplifiers were fabricated and tested to validate the positive feedback design methodology. Simulation shows that 98.4% of positive feedback amplifiers have improved gain over the baseline differential amplifier with an average improvement in gain of 10.3 dB. Silicon measurements of the amplifier gain show improvements of 17.1 dB on average. Similar to the application of negative feedback, gain improvement is achieved at the cost of frequency response. The gain-bandwidth product of the amplifier is reduced by an average of 18.4 GHz from 44.6 GHz. The circuitry required to implement this technique represent a meager 6% increase in silicon area from 460 μm2 to 488 μm2

Distributed Modeling Approach for Electrical and Thermal Analysis of High-Frequency Transistors

The research conducted in this dissertation is focused on developing modeling approaches for analyzing high-frequency transistors and present solutions for optimizing the device output power and gain. First, a literature review of different transistor types utilized in high-frequency regions is conducted and gallium nitride high electron mobility transistor is identified as the promising device for these bands. Different structural configurations and operating modes of these transistors are explained, and their applications are discussed. Equivalent circuit models and physics-based models are also introduced and their limitations for analyzing the small-signal and large-signal behavior of these devices are explained. Next, a model is developed to investigate the thermal properties of different semiconductor substrates. Heat dissipation issues associated with some substrate materials, such as sapphire, silicon, and silicon carbide are identified, and thinning the substrates is proposed as a preliminary solution for addressing them. This leads to a comprehensive and universal approach to increase the heat dissipation capabilities of any substrate material and 2X-3X improvement is achieved according to this novel technique. Moreover, for analyzing the electrical behavior of these devices, a small-signal model is developed to examine the operation of transistors in the linear regions. This model is obtained based on an equivalent circuit which includes the distributed effects of the device at higher frequency bands. In other words, the wave propagation effects and phase velocity mismatches are considered when developing the model. The obtained results from the developed simulation tool are then compared with the measurements and excellent agreement is achieved between the two cases, which serves as the proof for validation. Additionally, this model is extended to predict and analyze the nonlinear behavior of these transistors and the developed tool is validated according to the obtained large-signal analysis results from measurement. Based on the developed modeling approach, a novel fabrication technique is also proposed which ensures the high-frequency operability of current devices with the available fabrication technologies, without forfeiting the gain and output power. The technical details regarding this approach and a sample configuration of the electrode model for the transistor based on the proposed design are also provided

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Implémentation de PCM (Process Compact Models) pour l’étude et l’amélioration de la variabilité des technologies CMOS FDSOI avancées

Recently, the race for miniaturization has seen its growth slow because of technological challenges it entails. These barriers include the increasing impact of the local variability and processes from the increasing complexity of the manufacturing process and miniaturization, in addition to the difficult of reducing the channel length. To address these challenges, new architectures, very different from the traditional one (bulk), have been proposed. However these new architectures require more effort to be industrialized. Increasing complexity and development time require larger financial investments. In fact there is a real need to improve the development and optimization of devices. This work gives some tips in order to achieve these goals. The idea to address the problem is to reduce the number of trials required to find the optimal manufacturing process. The optimal process is one that results in a device whose performance and dispersion reach the predefined aims. The idea developed in this thesis is to combine TCAD tool and compact models in order to build and calibrate what is called PCM (Process Compact Model). PCM is an analytical model that establishes linkages between process and electrical parameters of the MOSFET. It takes both the benefits of TCAD (since it connects directly to the process parameters electrical parameters) and compact (since the model is analytic and therefore faster to calculate). A sufficiently robust predictive and PCM can be used to optimize performance and overall variability of the transistor through an appropriate optimization algorithm. This approach is different from traditional development methods that rely heavily on scientific expertise and successive tests in order to improve the system. Indeed this approach provides a deterministic and robust mathematical framework to the problem. The concept was developed, tested and applied to transistors 28 and 14 nm FD-SOI and to TCAD simulations. The results are presented and recommendations to implement it at industrial scale are provided. Some perspectives and applications are likewise suggested.Récemment, la course à la miniaturisation a vue sa progression ralentir à cause des défis technologiques qu’elle implique. Parmi ces obstacles, on trouve l’impact croissant de la variabilité local et process émanant de la complexité croissante du processus de fabrication et de la miniaturisation, en plus de la difficulté à réduire la longueur du canal. Afin de relever ces défis, de nouvelles architectures, très différentes de celle traditionnelle (bulk), ont été proposées. Cependant ces nouvelles architectures demandent plus d’efforts pour être industrialisées. L’augmentation de la complexité et du temps de développement requièrent de plus gros investissements financier. De fait il existe un besoin réel d’améliorer le développement et l’optimisation des dispositifs. Ce travail donne quelques pistes dans le but d’atteindre ces objectifs. L’idée, pour répondre au problème, est de réduire le nombre d’essai nécessaire pour trouver le processus de fabrication optimal. Le processus optimal est celui qui conduit à un dispositif dont les performances et leur dispersion atteignent les objectifs prédéfinis. L’idée développée dans cette thèse est de combiner l’outil TCAD et les modèles compacts dans le but de construire et calibrer ce que l’on appelle un PCM (Process Compact Model). Un PCM est un modèle analytique qui établit les liens entre les paramètres process et électriques du MOSFET. Il tire à la fois les bénéfices de la TCAD (puisqu’il relie directement les paramètres process aux paramètres électriques) et du modèle compact (puisque le modèle est analytique et donc rapide à calculer). Un PCM suffisamment prédictif et robuste peut être utilisé pour optimiser les performances et la variabilité globale du transistor grâce à un algorithme d’optimisation approprié. Cette approche est différente des méthodes de développement classiques qui font largement appel à l’expertise scientifique et à des essais successifs dans le but d’améliorer le dispositif. En effet cette approche apporte un cadre mathématique déterministe et robuste au problème.Le concept a été développé, testé et appliqué aux transistors 28 et 14 nm FD-SOI ainsi qu’aux simulations TCAD. Les résultats sont exposés ainsi que les recommandations nécessaires pour implémenter la technique à échelle industrielle. Certaines perspectives et applications sont de même suggérées

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

13th Annual Review of Progress in Applied Computational Electromagnetics at the Naval Postgraduate School, Monterey, CA, March 17-21, 1997, Conference Proceedings Volumes I & II

Includes Volumes 1 &

Technology 2001: The Second National Technology Transfer Conference and Exposition, volume 2

Proceedings of the workshop are presented. The mission of the conference was to transfer advanced technologies developed by the Federal government, its contractors, and other high-tech organizations to U.S. industries for their use in developing new or improved products and processes. Volume two presents papers on the following topics: materials science, robotics, test and measurement, advanced manufacturing, artificial intelligence, biotechnology, electronics, and software engineering

Reports to the President

A compilation of annual reports for the 1985-1986 academic year, including a report from the President of the Massachusetts Institute of Technology, as well as reports from the academic and administrative units of the Institute. The reports outline the year's goals, accomplishments, honors and awards, and future plans