Methodologies For Thermal Analysis In Single Die And Stacked Dies Electronic Packaging

Thermal analysis in single die and stacked dies electronic packaging for portable communication devices is very important due to lack of real estate for active cooling. Recent research had focused on active cooling and neglected the low cost passive cooling by optimizing the architecture of package structure and material selection. Stacked dies electronic package is an economical and good electrical performance innovation but inherent thermal problems which caused by thermal crosstalk. Recent methodology for numerical method and measurement method for thermal analysis in QFN and stacked dies LBGA is labor intensive, needs huge amount of investment and requires expert’s knowledge

Prediksi Harga Emas Menggunakan Metode Neural Network Backropagation Algoritma Conjugate Gradient

Artificial Neural Network Backpropagation is known as one of the most reliable methods of predicting. The algorithm used in this research is Conjugate Gradient algorithm, with gold data data of input data for training data. The price of gold becomes an issue in the market, as a precious metal that can be used for investment is very interesting to make a gold price prediction application. Gold prices continue to increase in the world market, making investors interested to invest in this precious metal. The application of gold price prediction will be very useful for investors of precious metals. Gold price data used in this research is daily data, taken 3 (three) last year and divided into test data and data testing. Test data is used to generate new weights for data testing. The parameters used in the measurement of evaluation of predicted results from Conjugate Gradient algorithm Artificial Neural Network Backpropagation method is Meant Square Error (MSE), where the result of MSE from this research is 0.031365

Constraint-Aware, Scalable, and Efficient Algorithms for Multi-Chip Power Module Layout Optimization

Moving towards an electrified world requires ultra high-density power converters. Electric vehicles, electrified aerospace, data centers, etc. are just a few fields among wide application areas of power electronic systems, where high-density power converters are essential. As a critical part of these power converters, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the emerging MCPM layouts is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with ongoing research toward enhanced capabilities to speed up the optimized MCPM layout design process. This dissertation presents the PowerSynth progression timeline with the methodology updates and corresponding critical results compared to v1.1. The first released version (v1.1) of PowerSynth demonstrated the benefits of layout abstraction, and reduced-order modeling techniques to perform rapid optimization of the MCPM module compared to the traditional, manual, and iterative design approach. However, that version is limited by several key factors: layout representation technique, layout generation algorithms, iterative design-rule-checking (DRC), optimization algorithm candidates, etc. To address these limitations, and enhance PowerSynth’s capabilities, constraint-aware, scalable, and efficient algorithms have been developed and implemented. PowerSynth layout engine has evolved from v1.3 to v2.0 throughout the last five years to incorporate the algorithm updates and generate all 2D/2.5D/3D Manhattan layout solutions. These fundamental changes in the layout generation methodology have also called for updates in the performance modeling techniques and enabled exploring different optimization algorithms. The latest PowerSynth 2 architecture has been implemented to enable electro-thermo-mechanical and reliability optimization on 2D/2.5D/3D MCPM layouts, and set up a path toward cabinet-level optimization. PowerSynth v2.0 computer-aided design (CAD) flow has been hardware-validated through manufacturing and testing of an optimized novel 3D MCPM layout. The flow has shown significant speedup compared to the manual design flow with a comparable optimization result

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output

Book of abstracts of the 14th International Symposium of Croatian Metallurgical Society - SHMD \u272020, Materials and metallurgy

Book of abstracts of the 14th International Symposium of Croatian Metallurgical Society - SHMD \u272020, Materials and metallurgy held in Šibenik, Croatia, June 21-26, 2020. Abstracts are organized in four sections: Materials - section A; Process metallurgy - Section B; Plastic processing - Section C and Metallurgy and related topics - Section D

Mechanics of Non Planar Interfaces in Flip-Chip Interconnects

With the continued proliferation of low cost, portable consumer electronic products with greater functionality, there is increasing demand for electronic packaging that is smaller, lighter and less expensive. Flip chip is an essential enabling technology for these products. The electrical connection between the chip I/O and substrate is achieved using conductive materials, such as solder, conductive epoxy, metallurgy bump (e.g., gold) and anisotropic conductive adhesives. The interconnect regions of flip-chip packages consists of highly dissimilar materials to meet their functional requirements. The mismatches in properties, contact morphology and crystal orientation at those material interfaces make them vulnerable to failure through delamination and crack growth under various loading patterns. This study encompasses contact between deformable bodies, bonding at the asperities and fracture properties at interfaces formed by the interconnects of flip-chip packages. This is achieved through experimentation and modeling at different length scales, to be able to capture the detailed microstructural features and contact mechanics at interfaces typically found in electronic systems

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.Siirretty Doriast

Ferrite-based micro-inductors for power systems on chip : from material elaboration to inductor optimisation

Les composants passifs intégrés sont des éléments clés pour les futures alimentations sur puce, compactes et présentant des performances améliorées: haut rendement et forte densité de puissance. L'objectif de ce travail de thèse est d'étudier les matériaux et la technologie pour réaliser de bobines à base de ferrite, intégrées sur silicium, avec des faibles empreintes (<4 mm ²) et de faible épaisseur (<250 µm). Ces bobines, dédiées à la conversion de puissance (˜ 1 W) doivent présenter une forte inductance spécifique et un facteur de qualité élevé dans la gamme de fréquence visée (5-10 MHz). Des ferrites de NiZn ont été sélectionnées comme matériaux magnétiques pour le noyau des bobines en raison de leur forte résistivité et de leur perméabilité stable dans la gamme de fréquence visée. Deux techniques sont développées pour les noyaux de ferrite: la sérigraphie d'une poudre synthétisée au laboratoire et la découpe automatique de films de ferrite commerciaux, suivi dans chaque cas du frittage et le placement sur les conducteurs pour former une bobine rectangulaire. Des bobines tests ont été réalisées dans un premier temps afin que la caractérisation puisse être effectuée : les propriétés magnétiques du noyau de ferrite notamment les pertes volumiques dans le noyau sont ainsi extraites. L'équation de Steinmetz a permis de corréler les courbes de pertes mesurées avec des expressions analytiques en fonction de la fréquence et de l'induction. La deuxième phase de la thèse est l'optimisation de la conception de la micro-bobine à base de ferrite, en tenant compte des pertes attendues. L'algorithme générique est utilisé pour optimiser les dimensions de la bobine avec pour objectif ; la minimisation des pertes et l'obtention de la valeur d'inductance spécifique souhaitée, sous faible polarisation en courant. La méthode des éléments finis pour le magnétisme FEMM est utilisée pour modéliser le comportement électromagnétique du composant. La deuxième série de prototypes a été réalisée afin de valider la méthode d'optimisation. En perspective, les procédés de photolithographie de résine épaisse et le dépôt électrolytique sont en cours de développement pour réaliser les enroulements de cuivre épais autour des noyaux de ferrite optimisés et ainsi former le composant complet.On-chip inductors are key passive elements for future power supplies on chip (PwrSoC), which are expected to be compact and show enhanced performance: high efficiency and high power density. The objective of this thesis work is to study the material and technology to realize small size (<4 mm²) and low profile (< 250 µm) ferrite-based on-chip inductor. This component is dedicated to low power conversion (˜ 1 W) and should provide high inductance density and high quality factor at medium frequency range (5-10 MHz). Fully sintered NiZn ferrites are selected as soft magnetic materials for the inductor core because of their high resistivity and moderate permeability stable in the frequencies range of interest. Two techniques are developed for the ferrite cores: screen printing of in-house made ferrite powder and cutting of commercial ferrite films, followed in each case by sintering and pick-and place assembling to form the rectangular toroid inductor. Test inductors were realized first so that the characterization could be carried out to study the magnetic properties of the ferrite core and the volumetric core losses. The core losses were fit from the measured curve with Steinmetz equation to obtain analytical expressions of losses versus frequency and induction. The second phase of the thesis is the design optimization for the on-chip ferrite based inductor, taking into account the expected losses. Genetic algorithm is employed to optimize the inductor design with the objective function as minimum losses and satisfying the specification on the inductance values under weak current-bias condition. Finite element method for magnetics FEMM is used as a tool to calculate inductance and losses. The second run of prototypes was done to validate the optimization method. In perspective, processes of thick-photoresist photolithography and electroplating are being developed to realize the completed thick copper windings surrounding ferrite cores