Power distribution design for high-density packages

This thesis describes the design of a high-density power distribution system. Properties of impedances of power distribution systems are examined. Impedances are classified as self and trans-impedances. These properties are then used to save simulation time, which is a big factor for power distribution system design. Time domain models are extracted for the test cases. A novel 2D-3D technique of placing decoupling capacitors is demonstrated that is based on the effectiveness of the capacitor at that location. The power distribution system acts as a cavity resonator supporting discrete modes that vary with distance. Each capacitor is placed at the physical location where it has maximum impact on corresponding system modes. Targeting the modes at the ports where they are dominant using decoupling capacitors reduces trans-impedances. This technique is extended to the entire surface of the power distribution system using just a single set of simulations. This thesis presents a novel 2D-3D approach of designing high-density boards having chips with multiple power connections without having to go through lengthy tedious simulations

On-Chip Digital Decoupling Capacitance Methodology

Signal integrity has become a major problem in digital IC design. One cause of this problem is device scaling which results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. Reductions in feature size also result in increased clock speeds leading to many different high frequency noise producing components. As on-chip area increases to allow for more computational capability, so does the amount of digital logic to be placed, magnifying the effects of noisy interconnect structures. Supply noise, modeled as AV = Ldi/dt , is caused by rapid current spikes during a rise or fall time. Decoupling capacitors often fill empty on-chip space for the purpose of limiting this noise. This work introduces a novel methodology that attempts to quantify and locate decoupling capacitors within a power distribution network. The bondwire attached on the periphery of the face of the die is taken to be the dominant source of inductance. It is shown that distributing capacitance closer to the switching elements is most effective at reducing supply noise. A chip has been designed using TSMC 90 nm technology that implements the ideas presented in this work. Simulation results show that noise fluctuations are high enough such that random placement of decoupling capacitance is not effective for large digital structures. The amount of interconnect generated on-chip noise increases with area, resulting in the need for an optimal decoupling scheme. As scaling continues, supply voltages and noise margins will decrease, creating the need for a robust decoupling capacitance methodology

A physics-based pi pre-layout tool for PCB PDN design

With increasingly stringent requirements for lower voltage supply, and higher density in PCB PDN design, now integrity (PI) is an increasingly important aspect that must be considered. A pre-layout tool based on the Cavity Model and Boundary Element Method is built to automatically achieve a specified target impedance for a multi-layered Printed Circuit Board (PCB) Power Distribution Network (PDN) design with a minimal number of decoupling capacitors. The pre-work about the post-layout design and analysis is proposed and the guidelines for creating a decoupling capacitors network with better performance has been built. With limit inputs, physical limitations for the minimal impedance that can be achieved in PDN system are calculated first to determine if a design is physically realizable and provide feedback to the user. The decoupling capacitor location will be determined by physics. Then a special decoupling capacitor selection algorithm through poles and zeros is utilized to determine which decoupling capacitor from a library should be added. Finally, the target impedance could be achieved using the minimum number of decoupling capacitors. Genetic algorithm is utilized to verify the performance and time cost of the new designed algorithm and several industry designs are used to verify the calculation result. The process is quite time-saving and convenient, and allows the user to do design discovery quickly, and determine the limiting factors under different conditions. --Abstract, page iii

EMI reduction on high-speed PCB using electromagnetic bandgap structure

The need for high-speed printed circuit board design whilst maintaining signal integrity and EMC standards have increased over the years in the modern integrated circuitry field. The use of electromagnetic bandgap structures (EBGs) have been demonstrated to provide excellent reduction of electromagnetic interference (EMI). In this study, a three by three planar of spiral, with and without patch were designed, simulated and fabricated on a low-cost FR4 substrate with permittivity of 4.3 and thickness of 1.6 mm. The designs of spiral EBGs with and without patch have the dimensions of 36 mm x 36 mm covering 9 unit cells. The performance of the designed EBGs were simulated and measured experimentally, and it was found to be in acceptable agreement. It was found that the spiral EBG without patch experienced a bandgap that covers from 4.5 to 6.3 GHz by using a dispersion diagram. Conversely, the bandgap for the spiral EBG with patch structure was found to be from 4.5 to 7.8 GHz with wider bandwidth. Owing to the desirable results demonstrated by the spiral EBG design with patch, it was then integrated into the high-speed circuit design to suppress the EMI emitted by the board. In this work, two low and three high-speed PCB designs were fabricated to track the desired EMI levels above 4.5 GHz. The third design of the high-speed PCB emitted the highest radiation emission (4.54 GHz) was selected for integration. The spiral EBG with patch structure successfully suppressed the EMI that occur at 4.54 GHz. Its effectiveness further suggests that the proposed EBG spiral with patch structure design is appropriate for EMI suppression that may occur from 4.5 to 7.8 GHz

Via transition modeling and charge replenishment of the power delivery network in multilayer PCBs

In the first article of this thesis, the charge delivery in the power distribution network for printed circuit board has been analyzed in the time-domain. Performing all the simulations and analyzing the PDN physics and modeling, I contributed to a better understanding of the time-domain decoupling mechanism. The second paper studies the noise coupling sing a segmentation approach combined with a via-to-antipad capacitance model and a plane-pair cavity model. Building equivalent circuit models as well as analyzing design strategies, I contributed to a new approach for the PDN analysis in multilayer PCBs. The third article discusses how to estimate the amount of current needed for large ICs and how to evaluate the amount of noise voltage due to this current draw. After accurate discussion of the design strategies, I modeled and simulated the free evolution of a charged PCB with and without decoupling capacitors. The depletion of charges stored between the power buses in time and frequency-domain has been investigated as a function of the plane thickness, SMT decoupling closeness in the fourth paper. With my contribution, the time and frequency-domain in the PDN have been related using circuit approach. In the fifth paper, I analyzed a 26-layer printed circuit board performing milling, measurements and building circuit models. It is the first time that the segmentation approach has been used for differential geometry. In addition, Debye materials have been implemented in the cavity model --Abstract, page iv

Power distribution network inductance calculation, transient current measurement and conductor surface roughness extraction

The first part in the thesis discussed the modeling of the mid-frequency inductance for Zpp type plane pairs in power distribution networks (PDN). It is a key step for the placement of the decoupling capacitors. This paper gives an efficient approach for the calculation of the inductance for different capacitor placements. The PEEC based formulations takes advantage of the opposite currents in the planes. This leads to compute time reductions and memory savings for both the element calculation and the matrix solve step. A formulation is used where placement of capacitors leads to only small changes in the circuit matrix. Comparisons with other models are made to validate our results. In the second part, the application of GMI probe to measure IC switching current. IC switching current is the main noise source of many power integrity issues in printed circuit boards. Accurate measurement of the current waveforms is critical for an effective power distribution network design. In this paper, using a giant magneto-impedance (GMI) probe for this purpose is studied. A side-band detection and demodulation system is built up to measure various time-domain waveforms using an oscilloscope. It is found that the GMI probes are potentially suitable for this kind of time-domain measurements, but probe designs and measurement setups need further improvements for this application. In the third part, the new Sigma rule to evaluate parameters of copper surface roughness in PCB layers is presented. This approach is based on taking SEM images of PCB cross-sections. The approach is automat [sic] zed [sic] by applying image processing tools and Matlab code to evaluate average roughness amplitude and period of roughness function. This information could be used in numerical and analytical modeling, as well as in the DERM method to separate rough conductor loss from dielectric loss --Abstract, page iv

Power Integrity Analysis For Jitter Characterization

Continuous improvements in the VLSI domain have enabled the integration of billions of transistors on the same die operating at frequencies in the gigahertz range. These advancements have brought upon the era of system-on-chip (SoC). Traditionally, analog ICs has been prone to device noise while digital ICs have typically not been the prime concern being considered as relatively immune to noise. With faster transition times and denser integration, the scenario wherein digital ICs were considered to be immune to noise has changed significantly. Drastic changes in the physical design of an IC and increase in the operating frequencies has immensely changed the classical understanding of noise in the new age complex ICs. Switching noise specifically has become a dominating criteria for high performance digital and mixed signal ICs. Voltage variations on the power/ground nodes of a circuit is a type of switching noise affecting digital and mixed-signal ICs. Therefore, power integrity (PI) has become a critical challenge that must be addressed at the system level considering the parasitic effects of package and board. In this work, a die, package and board modeling and co-simulation methodology is presented which can be easily integrated into a standard VLSI design flow. This methodology involves breaking down the system in multiple components and generating models for each component to observe individual performance. System level response can be seen by combining them together. This approach has been successfully exploited to guarantee the power integrity on an industrial design. This approach becomes successful in providing a systematic and a widely reusable method to estimate integrity issues before fabrication, thus exhibiting its worthiness as a design step in avoiding failures and re-spins