High level behavioural modelling of boundary scan architecture.

This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure

Measurements in 1149.4 environments - correcting the infrastructure switches influence

Measuring the values of discrete components frequently takes place during the test or debug phase of Printed Circuit Boards (PCB). This operation requires tools that are based on some access type. The shrinking geometries constrain the straightforward use of tools based on physical access. One of the aims of the IEEE1149.4 Std. is to facilitate those on-board measurements. This infrastructure relies on electronic access that includes high quality analog buses and a set of electronic switches, which enable to completely isolate a component under characterization, e.g. by injecting a known current and measuring the voltage across it. During this process, the infrastructure switches have a negative impact in the measurement accuracy. This paper analyses the measurement of one resistor in two situations: connected between a pin and ground and between two pins. The infrastructure switches that affect the measurement quality are identified and the upper limit of its systematic error is characterized. When the systematic error is completely defined then it is possible to remove its negative effect from the final result

Design for testability in hardware-software systems

Clearly, in today's complex systems, hardware and software approaches to DFT must work together to achieve a successful overall solution. The authors investigate existing and new concepts that may lead to a single design for test strategy in the futur

Boundary scan system design

Given the strong competition in digital design on the national and international levels, boundary scan devices are rapidly becoming a necessary as opposed to a convenient feature on integrated circuits. This thesis serves a dual purpose. First, it demonstrates how boundary scan devices can be used to increase the testability of a circuit and it presents several factors used to quantify the cost associated with the addition of boundary scan compatibility to digital designs. Cost tradeoffs are often the most intimidating hurdle for engineers to cross when deciding if boundary scan compatibility is worth the effort. Second, it demonstrates the use of the Tektronix LV500 (logic verifier) as a general testing tool, using boundary scan designs as examples. These examples provide an understanding of the function of boundary scan cells and the JTAG/1 149. 1 standard. The LV500, which is used by students in the Department of Computer Engineering and Microelectronic Engineering at RIT, is an indispensable tool for making critical timing measurements. It also allows a user to evaluate and step through simple as well as more complicated designs. It is my hope that this thesis and the tutorial provided will facilitate the use of the LV500 in future testing work performed in RIT\u27s center for Microelectronic and Computer Engineering clean room facilities. Upon following the example circuits described, one should become familiar with boundary scan terminology as well as the methodology used in designing such a system

New techniques for functional testing of microprocessor based systems

Electronic devices may be affected by failures, for example due to physical defects. These defects may be introduced during the manufacturing process, as well as during the normal operating life of the device due to aging. How to detect all these defects is not a trivial task, especially in complex systems such as processor cores. Nevertheless, safety-critical applications do not tolerate failures, this is the reason why testing such devices is needed so to guarantee a correct behavior at any time. Moreover, testing is a key parameter for assessing the quality of a manufactured product. Consolidated testing techniques are based on special Design for Testability (DfT) features added in the original design to facilitate test effectiveness. Design, integration, and usage of the available DfT for testing purposes are fully supported by commercial EDA tools, hence approaches based on DfT are the standard solutions adopted by silicon vendors for testing their devices. Tests exploiting the available DfT such as scan-chains manipulate the internal state of the system, differently to the normal functional mode, passing through unreachable configurations. Alternative solutions that do not violate such functional mode are defined as functional tests. In microprocessor based systems, functional testing techniques include software-based self-test (SBST), i.e., a piece of software (referred to as test program) which is uploaded in the system available memory and executed, with the purpose of exciting a specific part of the system and observing the effects of possible defects affecting it. SBST has been widely-studies by the research community for years, but its adoption by the industry is quite recent. My research activities have been mainly focused on the industrial perspective of SBST. The problem of providing an effective development flow and guidelines for integrating SBST in the available operating systems have been tackled and results have been provided on microprocessor based systems for the automotive domain. Remarkably, new algorithms have been also introduced with respect to state-of-the-art approaches, which can be systematically implemented to enrich SBST suites of test programs for modern microprocessor based systems. The proposed development flow and algorithms are being currently employed in real electronic control units for automotive products. Moreover, a special hardware infrastructure purposely embedded in modern devices for interconnecting the numerous on-board instruments has been interest of my research as well. This solution is known as reconfigurable scan networks (RSNs) and its practical adoption is growing fast as new standards have been created. Test and diagnosis methodologies have been proposed targeting specific RSN features, aimed at checking whether the reconfigurability of such networks has not been corrupted by defects and, in this case, at identifying the defective elements of the network. The contribution of my work in this field has also been included in the first suite of public-domain benchmark networks

Apoio à depuração e teste de circuitos mistos compatíveis com a norma IEEE1149.4

Tese de doutoramento. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto, Instituto Superior de Engenharia. Instituto Politécnico do Porto. 200

Processador dedicado para o teste em-circuito de blocos analógico-digitais em microssistemas integrados

Tese de mestrado. Engenharia Electrotécnica e de Computadores (Área de especialização em Informática e Sistemas Digitais). 2005. Faculdade de Engenharia. Universidade do Port