Nd:YAG development for spaceborne laser ranging system

The results of the development of a unique modelocked laser device to be utilized in future NASA space-based, ultraprecision laser ranger systems are summarized. The engineering breadboard constructed proved the feasibility of the pump-pulsed, actively modelocked, PTM Q-switched Nd:YAG laser concept for the generation of subnanosecond pulses suitable for ultra-precision ranging. The laser breadboard also included a double-pass Nd:YAG amplifier and provision for a Type II KD*P frequency doubler. The specific technical accomplishment was the generation of single 150 psec, 20-mJ pulses at 10 pps at a wavelength of 1.064 micrometers with 25 dB suppression of pre-and post-pulses

Development and Analysis of Non-Delay-Line Constant-Fraction Discriminator Timing Circuits, Including a Fully-Monolithic CMOS Implementation

A constant-fraction discriminator (CFD) is a time pick-off circuit providing time derivation that is insensitive to input-signal amplitude and, in some cases, input-signal rise time. CFD time pick-off circuits are useful in Positron Emission Tomography (PET) systems where Bismuth Germanate (BGO)/photomultiplier scintillation detectors detect coincident, 511-keV annihilation gamma rays. Time walk and noise-induced timing jitter in time pick-off circuits are discussed along with optimal and sub-optimal timing filters designed to minimize timing jitter. Additionally, the effects of scintillation-detector statistics on timing performance are discussed, and Monte Carlo analysis is developed to provide estimated timing and energy spectra for selected detector and time pick-off circuit configurations. The traditional delay-line CFD is then described with a discussion of deterministic (non statistical) performance and statistical Monte Carlo timing performance. A new class of non-delay-line CFD circuits utilizing lowpass- and/or allpass-filter delay-line approximations is then presented. The timing performance of these non-delay-line CFD circuits is shown to be comparable to traditional delay-line CFD circuits. Following the development and analysis of non-delay-line CFD circuits, a fully-monolithic, non-delay-line CFD circuit is presented which was fabricated in a standard digital, 2-μ, double-meta], double-poly, n-well CMOS process. The CMOS circuits developed include a low time walk comparator having a time walk of approximately 175 ps for input signals with amplitudes between 10-mV to 2000-mV and a rise time (10 - 90%) of 10 ns. Additionally, a fifth-order, continuous-time filter having a bandwidth of over 100 MHz was developed to provide CFD signal shaping without a delay line. The measured timing resolution (3.26 ns FWITh1, 6.50 ns FWTM) of the fully-monolithic, CMOS CFD is comparable to measured resolution (3.30 ns FWHM, 6.40 ns FWTM) of a commercial, discrete, bipolar CFD containing an external delay line. Each CFD was tested with a PET EGO/photomultiplier scintillation detector and a preamplifier having a 10-ns (10 - 90%) rise-time. The development of a fully-monolithic, CMOS CFD circuit, believed to be the first such reported development, is significant for PET and other systems that employ many front-end CFD time pick-off circuits

Application of advanced on-board processing concepts to future satellite communications systems: Bibliography

Abstracts are presented of a literature survey of reports concerning the application of signal processing concepts. Approximately 300 references are included

Process development of an analog/digital mixed-mode BiCMOS system at RIT

The development of an analog/digital mixed-mode BiCMOS process is presented. The process uses the RIT factory n-well CMOS process as its baseline process. The process is tailored to meet the requirements of an analog/digital system, while minimizing process complexity and maximizing compatibility with the established CMOS process. The process development includes determining the device requirements for the BiCMOS process, evaluating the established CMOS process, and integrating the additional process steps into the baseline process. TMA SUPREM III 1-D Process Analysis Program and RIT\u27s processing history are used as guidelines, keeping manufacturability an important issue. An integrated test chip is developed to measure the performance of the process and to compare measured results with modelling simulations. The test chip includes test structures for each masking level, along with test circuits that are designed using CMOS, bipolar, and BiCMOS technologies, which perform analog and digital functions. The process is implemented into the RIT factory, utilizing the WIPTRACK tracking system. Each processing step is entered into the system with complete instructions. Real-time measurement data is entered into the system at each step by operators under the supervision of the process engineer. Analysis of the test structures and test circuits will demonstrate the performance of the designed process

Instrumentation for observation of high frequency signals in the scanning electron microscope

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