Substrate noise analysis and techniques for mitigation in mixed-signal RF systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 151-158).Mixed-signal circuit design has historically been a challenge for several reasons. Parasitic interactions between analog and digital systems on a single die are one such challenge. Switching transients induced by digital circuits inject noise into the common substrate creating substrate noise. Analog circuits lack the large noise margins of digital circuits, thus making them susceptible to substrate voltage variations. This problem is exacerbated at higher frequencies as the effectiveness of standard isolation technique diminishes considerably. Historically, substrate noise was not a problem because each system was fabricated in its own package shielding it from such interactions. The work in this thesis spans all areas of substrate noise: generation, propagation, and reception. A set of guidelines in designing isolation structures was developed to assist designers in optimizing these structures for a particular application. Furthermore, the effect of substrate noise on two key components of the RF front end, the voltage controlled oscillator (VCO) and the low noise amplifier (LNA), was analyzed. Finally, a CAD tool (SNAT) was developed to efficiently simulate large digital designs to determine substrate noise performance.(cont.) Existing techniques have prohibitively long simulation times and are only suitable for final verification. Determination of substrate noise coupling during the design phase would be extremely beneficial to circuit designers who can incorporate the effect of the noise and re-design accordingly before fabrication. This would reduce the turn around time for circuits and prevent costly redesign. SNAT can be used at any stage of the design cycle to accurately predict (less than 12% error when compared to measurements) the substrate noise performance of any digital circuit with a large degree of computational efficiency.by Nisha Checka.Ph.D

I/O port macromodelling

3D electromagnetic modelling and simulation of various Printed Circuit Board (PCB) components is an important technique for characterizing the Signal Integrity (SI) and Electromagnetic Compatibility (EMC) issues present in a PCB. However, due to limited computational resource and the complexity of the integrated circuits, it is currently not possible to fully model a complete PCB system with 3D electromagnetic solvers. An effort has been made to fully model the PCB with all its components and their S-parameters has been derived so as to integrate these S-parameters in 1D, 2D static or quasi-static field solver or circuit solver tool. The novelty of this thesis is the development and verification of active circuit such as Input and Output buffers and passive channel components such as interconnects, via and connectors and deriving their S-parameters in order to model and characterize the complete PCB using 3D full field solver based on Transmission Line Matrix modelling (TLM) method. An integration of Input/Output (I/O) port in the 3D full field modelling method allows for modelling of the complete PCB system without being computationally expensive. This thesis presents a method for integration of Input/Output port in the 3D time domain modelling environment. Several software tools are available in the market which can characterize these PCBs in the frequency as well as the time domain using 1D, 2D techniques or using circuit solver such as spice. The work in this thesis looks at extending these 1D and 2D techniques for 3D Electromagnetic solvers in the time domain using the TLM technique for PCB analysis. The modelling technique presented in this thesis is based on in-house developed 3D TLM method along with a developed behavioral Integrated Circuit (IC) – macromodel. The method has been applied to a wide variety of PCB topologies along with a range of IC packages to fully validate the approach. The method has also been applied to show the switching effect arising out of the crosstalk in a logic device apart from modelling various discontinuities of PCB interconnects in the form of S11 and S21 parameters. The proposed novel TLM based technique has been selected based on simplification of its approach, electrical equivalence (rather than complex mathematical functions of Maxwell's electromagnetic theory), time domain analysis for transients in a PCB with an increased accuracy over other available methods in the literature. On the experimental side two, four and six layered PCBs with various interconnect discontinuities such as straight line, right angle, fan-out and via and IC packages such as SOT-23 (DBV), SC-70 (DCK) and SOT-553 (DRL) has been designed and manufactured. The modelling results have been verified with the experimental results of these PCBs and other commercial software such as HSPICE, CST design studio available in the market. While characterizing the SI issues, these modelling results can also help in analyzing conducted and radiated EMC/EMI problems to meet various EMC regulations such as CE, FCC around the world

I/O port macromodelling

3D electromagnetic modelling and simulation of various Printed Circuit Board (PCB) components is an important technique for characterizing the Signal Integrity (SI) and Electromagnetic Compatibility (EMC) issues present in a PCB. However, due to limited computational resource and the complexity of the integrated circuits, it is currently not possible to fully model a complete PCB system with 3D electromagnetic solvers. An effort has been made to fully model the PCB with all its components and their S-parameters has been derived so as to integrate these S-parameters in 1D, 2D static or quasi-static field solver or circuit solver tool. The novelty of this thesis is the development and verification of active circuit such as Input and Output buffers and passive channel components such as interconnects, via and connectors and deriving their S-parameters in order to model and characterize the complete PCB using 3D full field solver based on Transmission Line Matrix modelling (TLM) method. An integration of Input/Output (I/O) port in the 3D full field modelling method allows for modelling of the complete PCB system without being computationally expensive. This thesis presents a method for integration of Input/Output port in the 3D time domain modelling environment. Several software tools are available in the market which can characterize these PCBs in the frequency as well as the time domain using 1D, 2D techniques or using circuit solver such as spice. The work in this thesis looks at extending these 1D and 2D techniques for 3D Electromagnetic solvers in the time domain using the TLM technique for PCB analysis. The modelling technique presented in this thesis is based on in-house developed 3D TLM method along with a developed behavioral Integrated Circuit (IC) – macromodel. The method has been applied to a wide variety of PCB topologies along with a range of IC packages to fully validate the approach. The method has also been applied to show the switching effect arising out of the crosstalk in a logic device apart from modelling various discontinuities of PCB interconnects in the form of S11 and S21 parameters. The proposed novel TLM based technique has been selected based on simplification of its approach, electrical equivalence (rather than complex mathematical functions of Maxwell's electromagnetic theory), time domain analysis for transients in a PCB with an increased accuracy over other available methods in the literature. On the experimental side two, four and six layered PCBs with various interconnect discontinuities such as straight line, right angle, fan-out and via and IC packages such as SOT-23 (DBV), SC-70 (DCK) and SOT-553 (DRL) has been designed and manufactured. The modelling results have been verified with the experimental results of these PCBs and other commercial software such as HSPICE, CST design studio available in the market. While characterizing the SI issues, these modelling results can also help in analyzing conducted and radiated EMC/EMI problems to meet various EMC regulations such as CE, FCC around the world

Design and modelling of CMOS operational amplifiers.

by Chung-Yuk Or.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 95-[98]).Abstract also in Chinese.Chapter 1 --- Introduction --- p.1Chapter 2 --- Fully Differential CMOS Operational Amplifier Design --- p.4Chapter 2.1 --- Wide-Swing Current Mirror --- p.5Chapter 2.2 --- Wide-Swing Biasing Network --- p.8Chapter 2.3 --- Fully differential folded-cascode operational amplifier --- p.13Chapter 2.3.1 --- Small-Signal Analysis --- p.16Chapter 2.4 --- Gain-boost technique --- p.18Chapter 2.4.1 --- Frequency Response --- p.24Chapter 2.5 --- Common-Mode Feedback Network --- p.26Chapter 2.5.1 --- Continuous-Time CMFB Circuit --- p.27Chapter 2.5.2 --- Discrete-Time CMFB circuit --- p.33Chapter 2.6 --- Design Flow of the Operational Amplifier --- p.35Chapter 3 --- Physical Design of the Operational Amplifier --- p.39Chapter 3.1 --- Layout Level Design --- p.40Chapter 3.2 --- Layout Techniques --- p.42Chapter 3.3 --- Input Protection Circuitry --- p.47Chapter 4 --- Simulation Results --- p.49Chapter 4.1 --- Simulation of the Operational Amplifier --- p.49Chapter 4.2 --- Simulation of Auxiliary Amplifiers --- p.57Chapter 4.3 --- Simulation of the Common-Mode Feedback Circuit --- p.62Chapter 5 --- Measurement Results --- p.70Chapter 5.1 --- Transient Response Measurement --- p.70Chapter 5.2 --- Frequency Response Measurement --- p.74Chapter 5.3 --- Power Consumption Measurement --- p.78Chapter 5.4 --- Performance Evaluation --- p.81Chapter 6 --- Layout Driven Operational Amplifiers Macromodelling --- p.82Chapter 6.1 --- Motivations --- p.83Chapter 6.2 --- Methodology --- p.84Chapter 6.3 --- Macromodelling the operational amplifier --- p.85Chapter 6.4 --- Simulation Results --- p.88Chapter 6.5 --- Conclusions --- p.92Chapter 7 --- Conclusions --- p.93Bibliography --- p.95A Layout Diagrams and Chip Micrograph --- p.9

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Transient simulation of complex electronic circuits and systems operating at ultra high frequencies

The electronics industry worldwide faces increasingly difficult challenges in a bid to produce ultra-fast, reliable and inexpensive electronic devices. Electronic manufacturers rely on the Electronic Design Automation (EDA) industry to produce consistent Computer A id e d Design (CAD) simulation tools that w ill enable the design of new high-performance integrated circuits (IC), the key component of a modem electronic device. However, the continuing trend towards increasing operational frequencies and shrinking device sizes raises the question of the capability of existing circuit simulators to accurately and efficiently estimate circuit behaviour. The principle objective of this thesis is to advance the state-of-art in the transient simulation of complex electronic circuits and systems operating at ultra high frequencies. Given a set of excitations and initial conditions, the research problem involves the determination of the transient response o f a high-frequency complex electronic system consisting of linear (interconnects) and non-linear (discrete elements) parts with greatly improved efficien cy compared to existing methods and with the potential for very high accuracy in a way that permits an effective trade-off between accuracy and computational complexity. High-frequency interconnect effects are a major cause of the signal degradation encountered b y a signal propagating through linear interconnect networks in the modem IC. Therefore, the development of an interconnect model that can accurately and efficiently take into account frequency-dependent parameters of modem non-uniform interconnect is of paramount importance for state-of-art circuit simulators. Analytical models and models based on a set of tabulated data are investigated in this thesis. Two novel, h igh ly accurate and efficient interconnect simulation techniques are developed. These techniques combine model order reduction methods with either an analytical resonant model or an interconnect model generated from frequency-dependent sparameters derived from measurements or rigorous full-wave simulation. The latter part o f the thesis is concerned with envelope simulation. The complex mixture of profoundly different analog/digital parts in a modern IC gives rise to multitime signals, where a fast changing signal arising from the digital section is modulated by a slower-changing envelope signal related to the analog part. A transient analysis of such a circuit is in general very time-consuming. Therefore, specialised methods that take into account the multi-time nature o f the signal are required. To address this issue, a novel envelope simulation technique is developed. This technique combines a wavelet-based collocation method with a multi-time approach to result in a novel simulation technique that enables the desired trade-off between the required accuracy and computational efficiency in a simple and intuitive way. Furthermore, this new technique has the potential to greatly reduce the overall design cycle

Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors

The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2- and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance computed using our models and HSPICE simulations. Using a performance-driven design approach, the energy-optimized TiO2-based RRAM array consumes the least write energy (4.06 pJ/bit) and read energy (188 fJ/bit) when storing 3 bits/cell for 100 nsec write and 1 nsec read access times. Similarly, HfOx-based RRAM array consumes the least write energy (365 fJ/bit) and read energy (173 fJ/bit) when storing 3 bits/cell for 1 nsec write and 200 nsec read access times. On the logic side, we investigate the use of equalization techniques to improve the energy efficiency of digital sequential logic circuits in sub-threshold regime. We first propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors in digital logic designed in sub-threshold regime. This mitigation of timing errors can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path in a combinational logic block using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% (on average) in the sub-threshold regime. Overall, the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. We also propose a tunable adaptive feedback equalizer circuit that can be used with sequential digital logic to mitigate the process variation effects and reduce the dominant leakage energy component in sub-threshold digital logic circuits. For a 64-bit adder designed in 130 nm our proposed approach can reduce the normalized delay variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage. In addition, we present detailed energy-performance models of the adaptive feedback equalizer circuit. This work serves as a foundation for the design of robust, energy-efficient digital logic circuits in sub-threshold regime

Model order reduction techniques in microelectromechanics

Ph.DDOCTOR OF PHILOSOPH