Bulk-driven current mirrors

Bakalárska práca sa zaoberá problematikou princípu bulk-driven CMOS pre návrh niekolkých analogových obvodou. Princíp využíva substrátového hradla ako signálového vstupu k dosiahnutiu nízkého napájacieho napätia a nízkého príkonu pri zachovaní parametrou odpovedajúcich stavajúcim štruktúram. Cielom práce bolo za využitia tohoto princípu navrhnut prúdové zrkadlo s nízkym napájacím napätím a nízkim príkonom. V práci najdeme základné informácie o technológii bulk-driven a tranzistoroch MOSFET použitých v tejto technológii. Dalej sa oboznámime s rôznimi druhmy zapojení bulk-driven prudovích zrkadiel, ktoré sú porovnávané z konvencným gate-driven prúdovím zrkadlom. Tieto obvody sú modelované v programe Orcad Pspise.My bachelor’s thesis is about bulk-driven CMOS principle for several analog circuit projects. A substrate gate is used for signal input to achieve low supply voltage and low wattage while keeping parameters adequate to current structures. The goal of my work was to design current mirror with low supply voltage and low wattage with usage of this principle. In my work there are basic data about bulk-driven technology and MOFSET transistors used in this technology. My project contains different kinds of schemes of bulk-driven current mirrors which are compared with conventional gate-driven current mirror. These circuits are simulated in Orcard Pspise program.

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory

Low voltage, low power, bulk-driven amplifier

The importance of low voltage and low powered electronics is increasing with advances in medical electronics. This branch of electronics specifically requires low voltage and low power to make efficient innovative medical equipment. Low power electronics are also desirable because it conserves energy and power. This paper proposes a design of a differential in - differential our amplifier that uses a bulk-driven differential pair for the input pair. In addition, it also used bulk-driven current mirrors for the tail current sink and the active loads. The bulkdriven technique helps to achieve the low voltage design. 90nm CMOS technology was considered for the design but at the end SIGE 5AM process was chosen as it has low threshold voltage values maintaining good current - voltage characteristics. The software Cadence was used to simulate the design. A layout of the amplifier is out of the scope of this paper. A gain of 14 dB was achieved using a rail-to-rail voltage of 1V (0.5V to -0.5). The power dissipation was 102uW using 5pF capacitive loads. The values of the calculations match the values of the simulations quite well. Some of the differences can be explained by the lack of accurate knowledge of the some of the process parameters for the SIGE 5AM process. Overall, the design achieved its goals and a successful low voltage and low power fully differential amplifier was created with respectable gain. This amplifier can be used as an input stage for an operational amplifier

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS technologies

The International Technology Roadmap for Semiconductors predicts that the nominal power supply voltage, VDD, will fall to 0.7 V by the end of the bulk CMOS era. At that time, it is expected that the long-channel threshold voltage of a MOSFET, VT0, will rise to 35.5% of VDD in order to maintain acceptable off-state leakage characteristics in digital systems. Given the recent push for system-on-a-chip integration, this increasing trend in VT0/VDD poses a serious threat to the future of analog design because it causes traditional analog circuit topologies to experience progressively problematic signal swing limitations in each new process generation. To combat the process-scaling-induced signal swing limitations of analog circuitry, researchers have proposed the use of bulk-driven MOSFETs. By using the bulk terminal as an input rather than the gate, the bulk-driven MOSFET makes it possible to extend the applicability of any analog cell to extremely low power supply voltages because VT0 does not appear in the device\u27s input signal path. Since the viability of the bulk-driven technique was first investigated in a 2 um p-well process, there have been numerous reports of low-voltage analog designs incorporating bulk-driven MOSFETs in the literature - most of which appear in technologies with feature sizes larger than 0.18 um. However, as of yet, no effort has been undertaken to understand how sub-micron process scaling trends have influenced the performance of a bulk-driven MOSFET, let alone make the device more adaptable to the deca-nanometer technologies widely used in the analog realm today. Thus, to further the field\u27s understanding of the bulk-driven MOSFET, this dissertation aims to examine the implications of scaling the device into a standard 90 nm bulk CMOS process. This dissertation also describes how the major disadvantages of a bulk-driven MOSFET - i.e., its reduced intrinsic gain, its limited frequency response and its large layout area requirement - can be mitigated through modifications to the device\u27s vertical doping profile and well structure. To gauge the potency of the proposed process changes, an optimized n-type bulk-driven MOSFET has been designed in a standard 90 nm bulk CMOS process via the 2-D device simulator, ATLAS

Low-Voltage Analog Circuit Design Using the Adaptively Biased Body-Driven Circuit Technique

The scaling of MOSFET dimensions and power supply voltage, in conjunction with an increase in system- and circuit-level performance requirements, are the most important factors driving the development of new technologies and design techniques for analog and mixed-signal integrated circuits. Though scaling has been a fact of life for analog circuit designers for many years, the approaching 1-V and sub-1-V power supplies, combined with applications that have increasingly divergent technology requirements, means that the analog and mixed-signal IC designs of the future will probably look quite different from those of the past. Foremost among the challenges that analog designers will face in highly scaled technologies are low power supply voltages, which limit dynamic range and even circuit functionality, and ultra-thin gate oxides, which give rise to significant levels of gate leakage current. The goal of this research is to develop novel analog design techniques which are commensurate with the challenges that designers will face in highly scaled CMOS technologies. To that end, a new and unique body-driven design technique called adaptive gate biasing has been developed. Adaptive gate biasing is a method for guaranteeing that MOSFETs in a body-driven simple current mirror, cascode current mirror, or regulated cascode current source are biased in saturation—independent of operating region, temperature, or supply voltage—and is an enabling technology for high-performance, low-voltage analog circuits. To prove the usefulness of the new design technique, a body-driven operational amplifier that heavily leverages adaptive gate biasing has been developed. Fabricated on a 3.3-V/0.35-μm partially depleted silicon-onv-insulator (PD-SOI) CMOS process, which has nMOS and pMOS threshold voltages of 0.65 V and 0.85 V, respectively, the body-driven amplifier displayed an open-loop gain of 88 dB, bandwidth of 9 MHz, and PSRR greater than 50 dB at 1-V power supply

Complementary Bodydriving - A Low-voltage Analog Circuit Technique Realized In 0.35um SOI Process

This thesis presents a study of several analog circuit primitives that utilize the body terminal as a signal port to achieve low-voltage operation and high performance. Several issues relating to low-voltage applications as well as the trends of technology scaling in the near future are presented. Principles of the body-driven transistor for both PMOS and NMOS in PDSOI technology are described, and critical design considerations are discussed. The design of low-voltage analog primitives (cascode current mirror and differential pair) are described and analyzed in detail. A discussion of the design and analysis of a 4-quadrant analog multiplier is also presented. Prototyping and testing procedures are discussed and the results of the prototyped circuits are evaluated. Finally, a summary of the work is presented along with insights gained toward future research

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

Assessment of ecosystem integrity of lowland dipterocarp forest ecosystem using remote sensing

Ecosystem Integrity Index (EII) is a concept to determine the quality or the health of an ecosystem. The EII development can assist forest managers and decision makers in the conservation effort and forest management in Malaysia through the development of a simple and easy-to-adopt index. The aim of this study is to assess and evaluate the EII through the development of forest structure empirical models from remotely sensed data for lowland dipterocarp forest in Malaysia. The objectives of this study are: (i) to assess the structure and composition of lowland dipterocarp forest in Malaysia, (ii) to develop empirical model for estimating stand structure from remotely sensed data, and (iii) to derive the ecosystem integrity index for lowland dipterocarp forest. Tree Basal Area (BA), aboveground biomass (AGB) and volume plot from plot data were used as dependent variables, while remote sensing data from Landsat, Pleiades and LiDAR were used as independent variables for model development. Tree plot census was carried out from 17 to 19 May 2016, while remote sensing data acquisition dates for Landsat, Pleiades and LiDAR were 13 March 2016, 24 January 2015 and April 2015 respectively. Forest Structure Modeling was carried out by means of a correlation analysis with the calibration of dependent and independent data to select the most significant and accurate remote sensing variables to derive empiric equation (model), fitting stage to select the best model with the highest coefficient of determination (R2) and the lowest root mean square error ( RMSE) validation of the final selected. The Ecosystem Integrity Index was developed by the average percentage of the predicted BA, AGB and model volume. The EII was categorised at five integrity levels as high (81–100%), medium high (61–80%), moderate (41–60%), medium low (21–40%) and low (0–20%). A total of 1035 trees with diameter at breast height (DBH) of 5.0 cm and above were recorded in 69.115 ha sampling areas. The total trees recorded represented 150 species from 87 genera and 34 families. Shorea macroptera (Dipterocarpaceae), S. leprosula (Dipterocarpaceae) and S. parviflora (Dipterocarpaceae) are three dominant species, with Species Important Value Index (SIVi) of 6.49%, 6.23% and 5.51%, respectively. Dipterocarpaceae is the most dominant with Family Important Value Index (FIVi) of 33.54%. The developed final model is robust and consistent with high R2 with range of 0.84 to 0.87. The final models constructed for AGB, BA and volume value of R2 are 0.85, 0.84 and 0.87 respectively. The RMSE of AGB, BA and volume model are 53.1 Mg/ha, 3.54 m2/ha and 46.4 m3/ha, respectively. The overall stand AGB, BA and volume for Sungai Menyala Forest Reserve is 282.29 Mg/ha, 17.68 m2/ha and 239.51 m3/ha. An Ecosystem Integrity Index (EII) assessment has been successfully demonstrated by this study with production of practical, multi-scaled, flexible, adjustable and policy-relevant index. The overall EII of Sungai Menyala Forest Reserve is in Category 3, which shows that the area is within the medium value