Column-row addressing of thermo-optic phase shifters for controlling large silicon photonic circuits

We demonstrate a time-multiplexed row-column addressing scheme to drive thermo-optic phase shifters in a silicon photonic circuit. By integrating a diode in series with the heater, we can connect $N \times M$ heaters in an matrix topology to $N$ row and $M$ column lines. The heaters are digitally driven with pulse-width modulation, and time-multiplexed over different channels. This makes it possible to drive the circuit without digital-to-analog converters, and using only $M+N$ wires. We demonstrate this concept with a $1 \times 16$ power splitter tree with 15 thermo-optic phase shifters that are controlled in a $3 \times 5$ matrix, connected through 8 bond pads. This technique is especially useful in silicon photonic circuits with many tuners but limited space for electrical connections

A New 22 nm ULPLS Architecture to Detect 70 mV Minimum Input, Suitable for IOT Applications

Modern applications such as energy harvesting, signal monitoring in bio-medical sensing, portable point of care devices, etc. which involve state of the art mixed signal subsystems require robust ultra low power operation. Here in this work, a novel ultra low power level shifter (ULPLS) is proposed for sensing voltage signals in sub-threshold region. The proposed architecture is implemented in 22 nm technology using a dual power supply. The high and low supply voltages (VddH & VddL) are set as 0.8 V and 0.4 V respectively. The key design features of ULPLS include a current limiting PMOS diode, a voltage divider, and an enhanced pull up network. The ULPLS exhibits a low power dissipation of ~ 22.84 nW with a minimum ~ 70 mV detection of input signal. The robustness of the design has been examined via worst case and Monte Carlo analyses

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

This paper presents a solar energy harvesting power management using the high-efficiency switched capacitor DC-DC converter for biomedical implant applications. By employing an on-chip start-up circuit with parallel connected Photovoltaic (PV) cells, a small efficiency improvement can be obtained when compared with the traditional stacked photodiode methodology to boost the harvested voltage while preserving a single-chip solution. The PV cells have been optimised in the PC1D software and the optimal parameters modelled in the Cadence environment. A cross-coupled circuit with level shifter loop is also proposed to improve the overall step up voltage output and hybrid converter increases the start-up speed by 23.5%. The proposed system is implemented in a standard 0.18-μm CMOS technology. Simulation results show that the 4-phase start-up and cross coupled with level-shifter can achieve a maximum efficiency of 60%

Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant Devices

This paper presents a solar energy harvesting power management using the high-efficiency switched capacitor DC-DC converter for biomedical implant applications. By employing an on-chip start-up circuit with parallel connected Photovoltaic (PV) cells, a small efficiency improvement can be obtained when compared with the traditional stacked photodiode methodology to boost the harvested voltage while preserving a single-chip solution. The PV cells have been optimised in the PC1D software and the optimal parameters modelled in the Cadence environment. A cross-coupled circuit with level shifter loop is also proposed to improve the overall step up voltage output and hybrid converter increases the start-up speed by 23.5%. The proposed system is implemented in a standard 0.18-μm CMOS technology. Simulation results show that the 4-phase start-up and cross coupled with level-shifter can achieve a maximum efficiency of 60%

Advanced digital modulation: Communication techniques and monolithic GaAs technology

Communications theory and practice are merged with state-of-the-art technology in IC fabrication, especially monolithic GaAs technology, to examine the general feasibility of a number of advanced technology digital transmission systems. Satellite-channel models with (1) superior throughput, perhaps 2 Gbps; (2) attractive weight and cost; and (3) high RF power and spectrum efficiency are discussed. Transmission techniques possessing reasonably simple architectures capable of monolithic fabrication at high speeds were surveyed. This included a review of amplitude/phase shift keying (APSK) techniques and the continuous-phase-modulation (CPM) methods, of which MSK represents the simplest case

A low power 2 x 28 Gb/s electroabsorption modulator driver array with on-chip duobinary encoding

An integrated 2 x 28 Gb/s dual-channel duobinary driver IC is presented. Each channel has integrated coding blocks, transforming a non-return-to-zero input signal into a 3-level electrical duobinary signal to achieve an optical duobinary modulation. To the best of our knowledge this is the fastest modulator driver including on-chip duobinary encoding and precoding. Moreover, it only consumes 652 mW per channel at a differential output swing of 6 V-pp

Low cost autonomous lock-in amplifier for resistance/capacitance sensor measurements

This paper presents the design and experimental characterization of a portable high-precision single-phase lock-in instrument with phase adjustment. The core consists of an analog lock-in amplifier IC prototype, integrated in 0.18 µm CMOS technology with 1.8 V supply, which features programmable gain and operating frequency, resulting in a versatile on-chip solution with power consumption below 834 µW. It incorporates automatic phase alignment of the input and reference signals, performed through both a fixed-90° and a 4-bit digitally programmable phase shifter, specifically designed using commercially available components to operate at 1 kHz frequency. The system is driven by an Arduino YUN board, thus overall conforming a low-cost autonomous signal recovery instrument to determine, in real time, the electrical equivalent of resistive and capacitive sensors with a sensitivity of 16.3 µV/O @ erS < 3 % and 37 kV/F @ erS < 5 %, respectively

Design of Filter Using MOS Current Mode Logic

MCML (MOS Current Mode Logic) is a method used for the purpose of reducing the delay and power of the circuit. In high speed application this method is used to reduce the power. In this method the sleep transistor is inserted in series with the supply voltage (or) current source to reduce the power. Different power gating techniques are been used to reduce the static power and to improve the speed and efficiency of the circuit. In this paper, the filter can be designed by using MCML logic. The fourth order band pass filter by using MCML logic is introduced. In order to reduce the power and delay this method is proposed

A new high speed charge and high efficiency Li-Ion battery charger interface using pulse control technique

A new Li-Ion battery charger interface (BCI) using pulse control (PC) technique is designed and analyzed in this paper. Thanks to the use of PC technique, the main standards of the Li-Ion battery charger, i.e. fast charge, small surface area and high efficiency, are achieved. The proposed charger achieves full charge in forty-one minutes passing by the constant current (CC) charging mode which also included the start-up and the constant voltage mode (CV) charging mode. It designed, simulated and layouted which occupies a small size area 0.1 mm2 by using Taiwan Semiconductor Manufacturing Company 180 nm complementary metal oxide semi-conductor technology (TSMC 180 nm CMOS) technology in Cadence Virtuoso software. The battery voltage VBAT varies between 2.9 V to 4.35 V and the maximum battery current IBAT is 2.1 A in CC charging mode, according to a maximum input voltage VIN equal 5 V. The maximum charging efficiency reaches 98%

A 110/230 V AC and 15-400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer

This work presents an offline power supply with fully integrated power stage in 0.18 μ m high-voltage (HV) CMOS silicon on insulator (SOI). It supports both ac-dc and dc-dc conversion from 15-400 V input down to 3.3-10 V output and is optimized for applications below 300 mW such as the Internet of Things (IoT), smart home, and e-mobility. An active zero-crossing buffer enables on-chip integration of the HV buffer capacitor. Below 150 V, constant ON-time control is based on voltage intervals, sensed by ten HV threshold-detection circuits. Above 150 V, the converter operates in the resonant mode. It achieves a superior power density of 458 mW/cm3 and 84% peak efficiency