Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output

Advanced information processing system for advanced launch system: Hardware technology survey and projections

The major goals of this effort are as follows: (1) to examine technology insertion options to optimize Advanced Information Processing System (AIPS) performance in the Advanced Launch System (ALS) environment; (2) to examine the AIPS concepts to ensure that valuable new technologies are not excluded from the AIPS/ALS implementations; (3) to examine advanced microprocessors applicable to AIPS/ALS, (4) to examine radiation hardening technologies applicable to AIPS/ALS; (5) to reach conclusions on AIPS hardware building blocks implementation technologies; and (6) reach conclusions on appropriate architectural improvements. The hardware building blocks are the Fault-Tolerant Processor, the Input/Output Sequencers (IOS), and the Intercomputer Interface Sequencers (ICIS)

Analysis of terabit/second-class inter-chip parallel optoelectronic transceiver

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2010.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 89-92).Electrical copper-based interconnect has been suffering from fundamental physical loss mechanism and its current infrastructure will not be able to meet the increasing demand for data rates due to reaching the limit of the transmission bandwidth-distance product. Optical interconnect has been known as the candidate for taking over the obsolete electrical counterpart owing to the capability of transmitting data at high rates with low loss and the feasibility for parallel integration. Optoelectronic transceiver is one of the essential elements in optical interconnect system. This thesis scrutinizes a complete set of constituent technologies developed for a novel inter-chip parallel optoelectronic (OE) transceiver (known as Terabus transceiver) which is able to communicate data at the speed in the range of Terabit/second. A novel packaging hierarchy and a creative design for an optical coupling mechanism devised to bring high-level integration and high-speed performance to a final package have been analyzed: Two 4x12 arrays (each < 9 mm2) of CMOS transmitter and receiver ICs have been flip-chip bonded to a silicon carrier interposer of 1.2-cm2 size. Other two 4x12 arrays of OE devices (VCSELs and photodiodes) with comparable size are then flip-chip bonded to the corresponding CMOS arrays attached to the silicon carrier, forming the Optochip assembly. The Optochip is in interface with an Optocard by the flip-chip bonding process between the silicon carrier and an organic card patterned with 48 integrated waveguides at density of 16-channel/mm and total length of 30 cm. The 985-nm operating wavelength of the lasers allows a simple optical design with emission and illumination through arrays of relay lenses directly etched into the backside of the OE Ill-V substrate. A novel design of 45*-tilted and Au-coated mirrors fabricated in 125-ptmpitch acrylate waveguides is to perpendicularly couple the light in and out of the core of these Optocard waveguides. Per-channel performance of up to 20 Gb/s for transmitter and of up to 14 Gb/s for receiver have been realized. Lastly, the thesis has analyzed the market opportunity of the transceiver by reviewing the market situation, identifying contemporary competing technologies, assessing the market prospect and predicting the cost.by Nguyen Hoang Nguyen.M.Eng

High capacity photonic integrated switching circuits

As the demand for high-capacity data transfer keeps increasing in high performance computing and in a broader range of system area networking environments; reconfiguring the strained networks at ever faster speeds with larger volumes of traffic has become a huge challenge. Formidable bottlenecks appear at the physical layer of these switched interconnects due to its energy consumption and footprint. The energy consumption of the highly sophisticated but increasingly unwieldy electronic switching systems is growing rapidly with line rate, and their designs are already being constrained by heat and power management issues. The routing of multi-Terabit/second data using optical techniques has been targeted by leading international industrial and academic research labs. So far the work has relied largely on discrete components which are bulky and incurconsiderable networking complexity. The integration of the most promising architectures is required in a way which fully leverages the advantages of photonic technologies. Photonic integration technologies offer the promise of low power consumption and reduced footprint. In particular, photonic integrated semiconductor optical amplifier (SOA) gate-based circuits have received much attention as a potential solution. SOA gates exhibit multi-terahertz bandwidths and can be switched from a high-gain state to a high-loss state within a nanosecond using low-voltage electronics. In addition, in contrast to the electronic switching systems, their energy consumption does not rise with line rate. This dissertation will discuss, through the use of different kind of materials and integration technologies, that photonic integrated SOA-based optoelectronic switches can be scalable in either connectivity or data capacity and are poised to become a key technology for very high-speed applications. In Chapter 2, the optical switching background with the drawbacks of optical switches using electronic cores is discussed. The current optical technologies for switching are reviewed with special attention given to the SOA-based switches. Chapter 3 discusses the first demonstrations using quantum dot (QD) material to develop scalable and compact switching matrices operating in the 1.55µm telecommunication window. In Chapter 4, the capacity limitations of scalable quantum well (QW) SOA-based multistage switches is assessed through experimental studies for the first time. In Chapter 5 theoretical analysis on the dependence of data integrity as ultrahigh line-rate and number of monolithically integrated SOA-stages increases is discussed. Chapter 6 presents some designs for the next generation of large scale photonic integrated interconnects. A 16x16 switch architecture is described from its blocking properties to the new miniaturized elements proposed. Finally, Chapter 7 presents several recommendations for future work, along with some concluding remark

Analysis, synthesis, and fabrication of VLSI Si detector arrays for optoelectronic interconnections

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 141-145).by Edward Joseph Ouellette, III.M.S