736 research outputs found

    Reconfiguration for Fault Tolerance and Performance Analysis

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    Architecture reconfiguration, the ability of a system to alter the active interconnection among modules, has a history of different purposes and strategies. Its purposes develop from the relatively simple desire to formalize procedures that all processes have in common to reconfiguration for the improvement of fault-tolerance, to reconfiguration for performance enhancement, either through the simple maximizing of system use or by sophisticated notions of wedding topology to the specific needs of a given process. Strategies range from straightforward redundancy by means of an identical backup system to intricate structures employing multistage interconnection networks. The present discussion surveys the more important contributions to developments in reconfigurable architecture. The strategy here is in a sense to approach the field from an historical perspective, with the goal of developing a more coherent theory of reconfiguration. First, the Turing and von Neumann machines are discussed from the perspective of system reconfiguration, and it is seen that this early important theoretical work contains little that anticipates reconfiguration. Then some early developments in reconfiguration are analyzed, including the work of Estrin and associates on the fixed plus variable restructurable computer system, the attempt to theorize about configurable computers by Miller and Cocke, and the work of Reddi and Feustel on their restructable computer system. The discussion then focuses on the most sustained systems for fault tolerance and performance enhancement that have been proposed. An attempt will be made to define fault tolerance and to investigate some of the strategies used to achieve it. By investigating four different systems, the Tandern computer, the C.vmp system, the Extra Stage Cube, and the Gamma network, the move from dynamic redundancy to reconfiguration is observed. Then reconfiguration for performance enhancement is discussed. A survey of some proposals is attempted, then the discussion focuses on the most sustained systems that have been proposed: PASM, the DC architecture, the Star local network, and the NYU Ultracomputer. The discussion is organized around a comparison of control, scheduling, communication, and network topology. Finally, comparisons are drawn between fault tolerance and performance enhancement, in order to clarify the notion of reconfiguration and to reveal the common ground of fault tolerance and performance enhancement as well as the areas in which they diverge. An attempt is made in the conclusion to derive from this survey and analysis some observations on the nature of reconfiguration, as well as some remarks on necessary further areas of research

    DeSyRe: on-Demand System Reliability

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    The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

    Framework for simulation of fault tolerant heterogeneous multiprocessor system-on-chip

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    Due to the ever growing requirement in high performance data computation, current Uniprocessor systems fall short of hand to meet critical real-time performance demands in (i) high throughput (ii) faster processing time (iii) low power consumption (iv) design cost and time-to-market factors and more importantly (v) fault tolerant processing. Shifting the design trend to MPSOCs is a work-around to meet these challenges. However, developing efficient fault tolerant task scheduling and mapping techniques requires optimized algorithms that consider the various scenarios in Multiprocessor environments. Several works have been done in the past few years which proposed simulation based frameworks for scheduling and mapping strategies that considered homogenous systems and error avoidance techniques. However, most of these works inadequately describe today\u27s MPSOC trend because they were focused on the network domain and didn\u27t consider heterogeneous systems with fault tolerant capabilities; In order to address these issues, this work proposes (i) a performance driven scheduling algorithm (PD SA) based on simulated annealing technique (ii) an optimized Homogenous-Workload-Distribution (HWD) Multiprocessor task mapping algorithm which considers the dynamic workload on processors and (iii) a dynamic Fault Tolerant (FT) scheduling/mapping algorithm to employ robust application processing system. The implementation was accompanied by a heterogeneous Multiprocessor system simulation framework developed in systemC/C++. The proposed framework reads user data, set the architecture, execute input task graph and finally generate performance variables. This framework alleviates previous work issues with respect to (i) architectural flexibility in number-of-processors, processor types and topology (ii) optimized scheduling and mapping strategies and (iii) fault-tolerant processing capability focusing more on the computational domain; A set of random as well as application specific STG benchmark suites were run on the simulator to evaluate and verify the performance of the proposed algorithms. The simulations were carried out for (i) scheduling policy evaluation (ii) fault tolerant evaluation (iii) topology evaluation (iv) Number of processor evaluation (v) Mapping policy evaluation and (vi) Processor Type evaluation. The results showed that PD scheduling algorithm showed marginally better performance than EDF with respect to utilization, Execution-Time and Power factors. The dynamic Fault Tolerant implementation showed to be a viable and efficient strategy to meet real-time constraints without posing significant system performance degradation. Torus topology gave better performance than Tile with respect to task completion time and power factors. Executing highly heterogeneous Tasks showed higher power consumption and execution time. Finally, increasing the number of processors showed a decrease in average Utilization but improved task completion time and power consumption; Based on the simulation results, the system designer can compare tradeoffs between a various design choices with respect to the performance requirement specifications. In general, designing an optimized Multiprocessor scheduling and mapping strategy with added fault tolerant capability will enable to develop efficient Multiprocessor systems which meet future performance goal requirements. This is the substance of this work

    Self-adaptivity of applications on network on chip multiprocessors: the case of fault-tolerant Kahn process networks

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    Technology scaling accompanied with higher operating frequencies and the ability to integrate more functionality in the same chip has been the driving force behind delivering higher performance computing systems at lower costs. Embedded computing systems, which have been riding the same wave of success, have evolved into complex architectures encompassing a high number of cores interconnected by an on-chip network (usually identified as Multiprocessor System-on-Chip). However these trends are hindered by issues that arise as technology scaling continues towards deep submicron scales. Firstly, growing complexity of these systems and the variability introduced by process technologies make it ever harder to perform a thorough optimization of the system at design time. Secondly, designers are faced with a reliability wall that emerges as age-related degradation reduces the lifetime of transistors, and as the probability of defects escaping post-manufacturing testing is increased. In this thesis, we take on these challenges within the context of streaming applications running in network-on-chip based parallel (not necessarily homogeneous) systems-on-chip that adopt the no-remote memory access model. In particular, this thesis tackles two main problems: (1) fault-aware online task remapping, (2) application-level self-adaptation for quality management. For the former, by viewing fault tolerance as a self-adaptation aspect, we adopt a cross-layer approach that aims at graceful performance degradation by addressing permanent faults in processing elements mostly at system-level, in particular by exploiting redundancy available in multi-core platforms. We propose an optimal solution based on an integer linear programming formulation (suitable for design time adoption) as well as heuristic-based solutions to be used at run-time. We assess the impact of our approach on the lifetime reliability. We propose two recovery schemes based on a checkpoint-and-rollback and a rollforward technique. For the latter, we propose two variants of a monitor-controller- adapter loop that adapts application-level parameters to meet performance goals. We demonstrate not only that fault tolerance and self-adaptivity can be achieved in embedded platforms, but also that it can be done without incurring large overheads. In addressing these problems, we present techniques which have been realized (depending on their characteristics) in the form of a design tool, a run-time library or a hardware core to be added to the basic architecture

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    ํ•™์œ„๋…ผ๋ฌธ(๋ฐ•์‚ฌ)--์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› :๊ณต๊ณผ๋Œ€ํ•™ ์ปดํ“จํ„ฐ๊ณตํ•™๋ถ€,2020. 2. ํ•˜์ˆœํšŒ.์†Œํ”„ํŠธ์›จ์–ด ์„ค๊ณ„ ์ƒ์‚ฐ์„ฑ ๋ฐ ์œ ์ง€๋ณด์ˆ˜์„ฑ์„ ํ–ฅ์ƒ์‹œํ‚ค๊ธฐ ์œ„ํ•ด ๋‹ค์–‘ํ•œ ์†Œํ”„ํŠธ์›จ์–ด ๊ฐœ๋ฐœ ๋ฐฉ๋ฒ•๋ก ์ด ์ œ์•ˆ๋˜์—ˆ์ง€๋งŒ, ๋Œ€๋ถ€๋ถ„์˜ ์—ฐ๊ตฌ๋Š” ์‘์šฉ ์†Œํ”„ํŠธ์›จ์–ด๋ฅผ ํ•˜๋‚˜์˜ ํ”„๋กœ์„ธ์„œ์—์„œ ๋™์ž‘์‹œํ‚ค๋Š” ๋ฐ์— ์ดˆ์ ์„ ๋งž์ถ”๊ณ  ์žˆ๋‹ค. ๋˜ํ•œ, ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ์„ ๊ฐœ๋ฐœํ•˜๋Š” ๋ฐ์— ํ•„์š”ํ•œ ์ง€์—ฐ์ด๋‚˜ ์ž์› ์š”๊ตฌ ์‚ฌํ•ญ์— ๋Œ€ํ•œ ๋น„๊ธฐ๋Šฅ์  ์š”๊ตฌ ์‚ฌํ•ญ์„ ๊ณ ๋ คํ•˜์ง€ ์•Š๊ณ  ์žˆ๊ธฐ ๋•Œ๋ฌธ์— ์ผ๋ฐ˜์ ์ธ ์†Œํ”„ํŠธ์›จ์–ด ๊ฐœ๋ฐœ ๋ฐฉ๋ฒ•๋ก ์„ ์ž„๋ฒ ๋””๋“œ ์†Œํ”„ํŠธ์›จ์–ด๋ฅผ ๊ฐœ๋ฐœํ•˜๋Š” ๋ฐ์— ์ ์šฉํ•˜๋Š” ๊ฒƒ์€ ์ ํ•ฉํ•˜์ง€ ์•Š๋‹ค. ์ด ๋…ผ๋ฌธ์—์„œ๋Š” ๋ณ‘๋ ฌ ๋ฐ ๋ถ„์‚ฐ ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ์„ ๋Œ€์ƒ์œผ๋กœ ํ•˜๋Š” ์†Œํ”„ํŠธ์›จ์–ด๋ฅผ ๋ชจ๋ธ๋กœ ํ‘œํ˜„ํ•˜๊ณ , ์ด๋ฅผ ์†Œํ”„ํŠธ์›จ์–ด ๋ถ„์„์ด๋‚˜ ๊ฐœ๋ฐœ์— ํ™œ์šฉํ•˜๋Š” ๊ฐœ๋ฐœ ๋ฐฉ๋ฒ•๋ก ์„ ์†Œ๊ฐœํ•œ๋‹ค. ์šฐ๋ฆฌ์˜ ๋ชจ๋ธ์—์„œ ์‘์šฉ ์†Œํ”„ํŠธ์›จ์–ด๋Š” ๊ณ„์ธต์ ์œผ๋กœ ํ‘œํ˜„ํ•  ์ˆ˜ ์žˆ๋Š” ์—ฌ๋Ÿฌ ๊ฐœ์˜ ํƒœ์Šคํฌ๋กœ ์ด๋ฃจ์–ด์ ธ ์žˆ์œผ๋ฉฐ, ํ•˜๋“œ์›จ์–ด ํ”Œ๋žซํผ๊ณผ ๋…๋ฆฝ์ ์œผ๋กœ ๋ช…์„ธํ•œ๋‹ค. ํƒœ์Šคํฌ ๊ฐ„์˜ ํ†ต์‹  ๋ฐ ๋™๊ธฐํ™”๋Š” ๋ชจ๋ธ์ด ์ •์˜ํ•œ ๊ทœ์•ฝ์ด ์ •ํ•ด์ ธ ์žˆ๊ณ , ์ด๋Ÿฌํ•œ ๊ทœ์•ฝ์„ ํ†ตํ•ด ์‹ค์ œ ํ”„๋กœ๊ทธ๋žจ์„ ์‹คํ–‰ํ•˜๊ธฐ ์ „์— ์†Œํ”„ํŠธ์›จ์–ด ์—๋Ÿฌ๋ฅผ ์ •์  ๋ถ„์„์„ ํ†ตํ•ด ํ™•์ธํ•  ์ˆ˜ ์žˆ๊ณ , ์ด๋Š” ์‘์šฉ์˜ ๊ฒ€์ฆ ๋ณต์žก๋„๋ฅผ ์ค„์ด๋Š” ๋ฐ์— ๊ธฐ์—ฌํ•œ๋‹ค. ์ง€์ •ํ•œ ํ•˜๋“œ์›จ์–ด ํ”Œ๋žซํผ์—์„œ ๋™์ž‘ํ•˜๋Š” ํ”„๋กœ๊ทธ๋žจ์€ ํƒœ์Šคํฌ๋“ค์„ ํ”„๋กœ์„ธ์„œ์— ๋งคํ•‘ํ•œ ์ดํ›„์— ์ž๋™์ ์œผ๋กœ ํ•ฉ์„ฑํ•  ์ˆ˜ ์žˆ๋‹ค. ์œ„์˜ ๋ชจ๋ธ ๊ธฐ๋ฐ˜ ์†Œํ”„ํŠธ์›จ์–ด ๊ฐœ๋ฐœ ๋ฐฉ๋ฒ•๋ก ์—์„œ ์‚ฌ์šฉํ•˜๋Š” ํ”„๋กœ๊ทธ๋žจ ํ•ฉ์„ฑ๊ธฐ๋ฅผ ๋ณธ ๋…ผ๋ฌธ์—์„œ ์ œ์•ˆํ•˜์˜€๋Š”๋ฐ, ๋ช…์„ธํ•œ ํ”Œ๋žซํผ ์š”๊ตฌ ์‚ฌํ•ญ์„ ๋ฐ”ํƒ•์œผ๋กœ ๋ณ‘๋ ฌ ๋ฐ ๋ถ„์‚ฐ ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ์„์—์„œ ๋™์ž‘ํ•˜๋Š” ์ฝ”๋“œ๋ฅผ ์ƒ์„ฑํ•œ๋‹ค. ์—ฌ๋Ÿฌ ๊ฐœ์˜ ์ •ํ˜•์  ๋ชจ๋ธ๋“ค์„ ๊ณ„์ธต์ ์œผ๋กœ ํ‘œํ˜„ํ•˜์—ฌ ์‘์šฉ์˜ ๋™์  ํ–‰ํƒœ๋ฅผ ๋‚˜ํƒ€๊ณ , ํ•ฉ์„ฑ๊ธฐ๋Š” ์—ฌ๋Ÿฌ ๋ชจ๋ธ๋กœ ๊ตฌ์„ฑ๋œ ๊ณ„์ธต์ ์ธ ๋ชจ๋ธ๋กœ๋ถ€ํ„ฐ ๋ณ‘๋ ฌ์„ฑ์„ ๊ณ ๋ คํ•˜์—ฌ ํƒœ์Šคํฌ๋ฅผ ์‹คํ–‰ํ•  ์ˆ˜ ์žˆ๋‹ค. ๋˜ํ•œ, ํ”„๋กœ๊ทธ๋žจ ํ•ฉ์„ฑ๊ธฐ์—์„œ ๋‹ค์–‘ํ•œ ํ”Œ๋žซํผ์ด๋‚˜ ๋„คํŠธ์›Œํฌ๋ฅผ ์ง€์›ํ•  ์ˆ˜ ์žˆ๋„๋ก ์ฝ”๋“œ๋ฅผ ๊ด€๋ฆฌํ•˜๋Š” ๋ฐฉ๋ฒ•๋„ ๋ณด์—ฌ์ฃผ๊ณ  ์žˆ๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ ์ œ์‹œํ•˜๋Š” ์†Œํ”„ํŠธ์›จ์–ด ๊ฐœ๋ฐœ ๋ฐฉ๋ฒ•๋ก ์€ 6๊ฐœ์˜ ํ•˜๋“œ์›จ์–ด ํ”Œ๋žซํผ๊ณผ 3 ์ข…๋ฅ˜์˜ ๋„คํŠธ์›Œํฌ๋กœ ๊ตฌ์„ฑ๋˜์–ด ์žˆ๋Š” ์‹ค์ œ ๊ฐ์‹œ ์†Œํ”„ํŠธ์›จ์–ด ์‹œ์Šคํ…œ ์‘์šฉ ์˜ˆ์ œ์™€ ์ด์ข… ๋ฉ€ํ‹ฐ ํ”„๋กœ์„ธ์„œ๋ฅผ ํ™œ์šฉํ•˜๋Š” ์›๊ฒฉ ๋”ฅ ๋Ÿฌ๋‹ ์˜ˆ์ œ๋ฅผ ์ˆ˜ํ–‰ํ•˜์—ฌ ๊ฐœ๋ฐœ ๋ฐฉ๋ฒ•๋ก ์˜ ์ ์šฉ ๊ฐ€๋Šฅ์„ฑ์„ ์‹œํ—˜ํ•˜์˜€๋‹ค. ๋˜ํ•œ, ํ”„๋กœ๊ทธ๋žจ ํ•ฉ์„ฑ๊ธฐ๊ฐ€ ์ƒˆ๋กœ์šด ํ”Œ๋žซํผ์ด๋‚˜ ๋„คํŠธ์›Œํฌ๋ฅผ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•ด ํ•„์š”๋กœ ํ•˜๋Š” ๊ฐœ๋ฐœ ๋น„์šฉ๋„ ์‹ค์ œ ์ธก์ • ๋ฐ ์˜ˆ์ธกํ•˜์—ฌ ์ƒ๋Œ€์ ์œผ๋กœ ์ ์€ ๋…ธ๋ ฅ์œผ๋กœ ์ƒˆ๋กœ์šด ํ”Œ๋žซํผ์„ ์ง€์›ํ•  ์ˆ˜ ์žˆ์Œ์„ ํ™•์ธํ•˜์˜€๋‹ค. ๋งŽ์€ ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ์—์„œ ์˜ˆ์ƒ์น˜ ๋ชปํ•œ ํ•˜๋“œ์›จ์–ด ์—๋Ÿฌ์— ๋Œ€ํ•ด ๊ฒฐํ•จ์„ ๊ฐ๋‚ดํ•˜๋Š” ๊ฒƒ์„ ํ•„์š”๋กœ ํ•˜๊ธฐ ๋•Œ๋ฌธ์— ๊ฒฐํ•จ ๊ฐ๋‚ด์— ๋Œ€ํ•œ ์ฝ”๋“œ๋ฅผ ์ž๋™์œผ๋กœ ์ƒ์„ฑํ•˜๋Š” ์—ฐ๊ตฌ๋„ ์ง„ํ–‰ํ•˜์˜€๋‹ค. ๋ณธ ๊ธฐ๋ฒ•์—์„œ ๊ฒฐํ•จ ๊ฐ๋‚ด ์„ค์ •์— ๋”ฐ๋ผ ํƒœ์Šคํฌ ๊ทธ๋ž˜ํ”„๋ฅผ ์ˆ˜์ •ํ•˜๋Š” ๋ฐฉ์‹์„ ํ™œ์šฉํ•˜์˜€์œผ๋ฉฐ, ๊ฒฐํ•จ ๊ฐ๋‚ด์˜ ๋น„๊ธฐ๋Šฅ์  ์š”๊ตฌ ์‚ฌํ•ญ์„ ์‘์šฉ ๊ฐœ๋ฐœ์ž๊ฐ€ ์‰ฝ๊ฒŒ ์ ์šฉํ•  ์ˆ˜ ์žˆ๋„๋ก ํ•˜์˜€๋‹ค. ๋˜ํ•œ, ๊ฒฐํ•จ ๊ฐ๋‚ด ์ง€์›ํ•˜๋Š” ๊ฒƒ๊ณผ ๊ด€๋ จํ•˜์—ฌ ์‹ค์ œ ์ˆ˜๋™์œผ๋กœ ๊ตฌํ˜„ํ–ˆ์„ ๊ฒฝ์šฐ์™€ ๋น„๊ตํ•˜์˜€๊ณ , ๊ฒฐํ•จ ์ฃผ์ž… ๋„๊ตฌ๋ฅผ ์ด์šฉํ•˜์—ฌ ๊ฒฐํ•จ ๋ฐœ์ƒ ์‹œ๋‚˜๋ฆฌ์˜ค๋ฅผ ์žฌํ˜„ํ•˜๊ฑฐ๋‚˜, ์ž„์˜๋กœ ๊ฒฐํ•จ์„ ์ฃผ์ž…ํ•˜๋Š” ์‹คํ—˜์„ ์ˆ˜ํ–‰ํ•˜์˜€๋‹ค. ๋งˆ์ง€๋ง‰์œผ๋กœ ๊ฒฐํ•จ ๊ฐ๋‚ด๋ฅผ ์‹คํ—˜ํ•  ๋•Œ์— ํ™œ์šฉํ•œ ๊ฒฐํ•จ ์ฃผ์ž… ๋„๊ตฌ๋Š” ๋ณธ ๋…ผ๋ฌธ์˜ ๋˜ ๋‹ค๋ฅธ ๊ธฐ์—ฌ ์‚ฌํ•ญ ์ค‘ ํ•˜๋‚˜๋กœ ๋ฆฌ๋ˆ…์Šค ํ™˜๊ฒฝ์œผ๋กœ ๋Œ€์ƒ์œผ๋กœ ์‘์šฉ ์˜์—ญ ๋ฐ ์ปค๋„ ์˜์—ญ์— ๊ฒฐํ•จ์„ ์ฃผ์ž…ํ•˜๋Š” ๋„๊ตฌ๋ฅผ ๊ฐœ๋ฐœํ•˜์˜€๋‹ค. ์‹œ์Šคํ…œ์˜ ๊ฒฌ๊ณ ์„ฑ์„ ๊ฒ€์ฆํ•˜๊ธฐ ์œ„ํ•ด ๊ฒฐํ•จ์„ ์ฃผ์ž…ํ•˜์—ฌ ๊ฒฐํ•จ ์‹œ๋‚˜๋ฆฌ์˜ค๋ฅผ ์žฌํ˜„ํ•˜๋Š” ๊ฒƒ์€ ๋„๋ฆฌ ์‚ฌ์šฉ๋˜๋Š” ๋ฐฉ๋ฒ•์œผ๋กœ, ๋ณธ ๋…ผ๋ฌธ์—์„œ ๊ฐœ๋ฐœ๋œ ๊ฒฐํ•จ ์ฃผ์ž… ๋„๊ตฌ๋Š” ์‹œ์Šคํ…œ์ด ๋™์ž‘ํ•˜๋Š” ๋„์ค‘์— ์žฌํ˜„ ๊ฐ€๋Šฅํ•œ ๊ฒฐํ•จ์„ ์ฃผ์ž…ํ•  ์ˆ˜ ์žˆ๋Š” ๋„๊ตฌ์ด๋‹ค. ์ปค๋„ ์˜์—ญ์—์„œ์˜ ๊ฒฐํ•จ ์ฃผ์ž…์„ ์œ„ํ•ด ๋‘ ์ข…๋ฅ˜์˜ ๊ฒฐํ•จ ์ฃผ์ž… ๋ฐฉ๋ฒ•์„ ์ œ๊ณตํ•˜๋ฉฐ, ํ•˜๋‚˜๋Š” ์ปค๋„ GNU ๋””๋ฒ„๊ฑฐ๋ฅผ ์ด์šฉํ•œ ๋ฐฉ๋ฒ•์ด๊ณ , ๋‹ค๋ฅธ ํ•˜๋‚˜๋Š” ARM ํ•˜๋“œ์›จ์–ด ๋ธŒ๋ ˆ์ดํฌํฌ์ธํŠธ๋ฅผ ํ™œ์šฉํ•œ ๋ฐฉ๋ฒ•์ด๋‹ค. ์‘์šฉ ์˜์—ญ์—์„œ ๊ฒฐํ•จ์„ ์ฃผ์ž…ํ•˜๊ธฐ ์œ„ํ•ด GDB ๊ธฐ๋ฐ˜ ๊ฒฐํ•จ ์ฃผ์ž… ๋ฐฉ๋ฒ•์„ ์ด์šฉํ•˜์—ฌ ๋™์ผ ์‹œ์Šคํ…œ ํ˜น์€ ์›๊ฒฉ ์‹œ์Šคํ…œ์˜ ์‘์šฉ์— ๊ฒฐํ•จ์„ ์ฃผ์ž…ํ•  ์ˆ˜ ์žˆ๋‹ค. ๊ฒฐํ•จ ์ฃผ์ž… ๋„๊ตฌ์— ๋Œ€ํ•œ ์‹คํ—˜์€ ODROID-XU4 ๋ณด๋“œ์—์„œ ์ง„ํ–‰ํ•˜์˜€๋‹ค.While various software development methodologies have been proposed to increase the design productivity and maintainability of software, they usually focus on the development of application software running on a single processing element, without concern about the non-functional requirements of an embedded system such as latency and resource requirements. In this thesis, we present a model-based software development method for parallel and distributed embedded systems. An application is specified as a set of tasks that follow a set of given rules for communication and synchronization in a hierarchical fashion, independently of the hardware platform. Having such rules enables us to perform static analysis to check some software errors at compile time to reduce the verification difficulty. Platform-specific program is synthesized automatically after mapping of tasks onto processing elements is determined. The program synthesizer is also proposed to generate codes which satisfies platform requirements for parallel and distributed embedded systems. As multiple models which can express dynamic behaviors can be depicted hierarchically, the synthesizer supports to manage multiple task graphs with a different hierarchy to run tasks with parallelism. Also, the synthesizer shows methods of managing codes for heterogeneous platforms and generating various communication methods. The viability of the proposed software development method is verified with a real-life surveillance application that runs on six processing elements with three remote communication methods, and remote deep learning example is conducted to use heterogeneous multiprocessing components on distributed systems. Also, supporting a new platform and network requires a small effort by measuring and estimating development costs. Since tolerance to unexpected errors is a required feature of many embedded systems, we also support an automatic fault-tolerant code generation. Fault tolerance can be applied by modifying the task graph based on the selected fault tolerance configurations, so the non-functional requirement of fault tolerance can be easily adopted by an application developer. To compare the effort of supporting fault tolerance, manual implementation of fault tolerance is performed. Also, the fault tolerance method is tested with the fault injection tool to emulate fault scenarios and inject faults randomly. Our fault injection tool, which has used for testing our fault-tolerance method, is another work of this thesis. Emulating fault scenarios by intentionally injecting faults is commonly used to test and verify the robustness of a system. To emulate faults on an embedded system, we present a run-time fault injection framework that can inject a fault on both a kernel and application layer of Linux-based systems. For injecting faults on a kernel layer, two complementary fault injection techniques are used. One is based on Kernel GNU Debugger, and the other is using a hardware breakpoint supported by the ARM architecture. For application-level fault injection, the GDB-based fault injection method is used to inject a fault on a remote application. The viability of the proposed fault injection tool is proved by real-life experiments with an ODROID-XU4 system.Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Contribution 6 1.3 Dissertation Organization 8 Chapter 2 Background 9 2.1 HOPES: Hope of Parallel Embedded Software 9 2.1.1 Software Development Procedure 9 2.1.2 Components of HOPES 12 2.2 Universal Execution Model 13 2.2.1 Task Graph Specification 13 2.2.2 Dataflow specification of an Application 15 2.2.3 Task Code Specification and Generic APIs 21 2.2.4 Meta-data Specification 23 Chapter 3 Program Synthesis for Parallel and Distributed Embedded Systems 24 3.1 Motivational Example 24 3.2 Program Synthesis Overview 26 3.3 Program Synthesis from Hierarchically-mixed Models 30 3.4 Platform Code Synthesis 33 3.5 Communication Code Synthesis 36 3.6 Experiments 40 3.6.1 Development Cost of Supporting New Platforms and Networks 40 3.6.2 Program Synthesis for the Surveillance System Example 44 3.6.3 Remote GPU-accelerated Deep Learning Example 46 3.7 Document Generation 48 3.8 Related Works 49 Chapter 4 Model Transformation for Fault-tolerant Code Synthesis 56 4.1 Fault-tolerant Code Synthesis Techniques 56 4.2 Applying Fault Tolerance Techniques in HOPES 61 4.3 Experiments 62 4.3.1 Development Cost of Applying Fault Tolerance 62 4.3.2 Fault Tolerance Experiments 62 4.4 Random Fault Injection Experiments 65 4.5 Related Works 68 Chapter 5 Fault Injection Framework for Linux-based Embedded Systems 70 5.1 Background 70 5.1.1 Fault Injection Techniques 70 5.1.2 Kernel GNU Debugger 71 5.1.3 ARM Hardware Breakpoint 72 5.2 Fault Injection Framework 74 5.2.1 Overview 74 5.2.2 Architecture 75 5.2.3 Fault Injection Techniques 79 5.2.4 Implementation 83 5.3 Experiments 90 5.3.1 Experiment Setup 90 5.3.2 Performance Comparison of Two Fault Injection Methods 90 5.3.3 Bit-flip Fault Experiments 92 5.3.4 eMMC Controller Fault Experiments 94 Chapter 6 Conclusion 97 Bibliography 99 ์š” ์•ฝ 108Docto

    Accelerated artificial neural networks on FPGA for fault detection in automotive systems

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    Modern vehicles are complex distributed systems with critical real-time electronic controls that have progressively replaced their mechanical/hydraulic counterparts, for performance and cost benefits. The harsh and varying vehicular environment can induce multiple errors in the computational/communication path, with temporary or permanent effects, thus demanding the use of fault-tolerant schemes. Constraints in location, weight, and cost prevent the use of physical redundancy for critical systems in many cases, such as within an internal combustion engine. Alternatively, algorithmic techniques like artificial neural networks (ANNs) can be used to detect errors and apply corrective measures in computation. Though adaptability of ANNs presents advantages for fault-detection and fault-tolerance measures for critical sensors, implementation on automotive grade processors may not serve required hard deadlines and accuracy simultaneously. In this work, we present an ANN-based fault-tolerance system based on hybrid FPGAs and evaluate it using a diesel engine case study. We show that the hybrid platform outperforms an optimised software implementation on an automotive grade ARM Cortex M4 processor in terms of latency and power consumption, also providing better consolidation
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