Heterojunction bipolar transistor technology for data acquisition and communication

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems

A leaky waveguide all-optical analog-to-digital converter

In this thesis we describe a novel all-optical analog-to-digital converter (AOADC) based on a leaky waveguide deflector. The principle of the spatial sampling AOADC is to convert an electrical signal to its corresponding optical deflection angle and then sample and quantize this angle in the spatial domain, instead of the amplitude domain. This AOADC is designed for broadband digital receivers working at frequencies above 20 GHz (a minimum 40 GS/s sampling rate) and provides a resolution higher than 6 bits. An original design based on GRISM (Grating and pRISM) is investigated for a high-resolution ADC implementation; and its challenges have been identified. The investigation provides a general model of spatial sampling AOADCs and highlights their advantages of immunity to optical intensity fluctuation. Later we proposed an AOADC that employs a leaky waveguide structure that is different from any other optical ADC. The AOADC consists of a sampler based on a mode-locked laser and a leaky waveguide deflector driven by traveling wave electrodes, a quantizer based on an integrated optical collector array and broadband photodetectors. These components provide the AOADC with a higher deflection angle and angular resolution resulting in high bit resolution without consuming significant power. The quantization of the deflection angle is done by a simple spatial quantizer that digitizes as well as encodes the signal simultaneously. A detailed design of the E-O deflector and the spatial quantizer has been analyzed and simulated; and some preliminary tests have been conducted. This thesis summarizes our contributions in designing and modeling this novel spatial sampling AOADC.Ph.D., Electrical Engineering -- Drexel University, 200

Miniaturized, low-voltage power converters with fast dynamic response

Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 216-224).This thesis introduces a two-stage architecture that combines the strengths of switched capacitor (SC) techniques (small size, light-load performance) with the high efficiency and regulation capability of switch-mode power converters. The resulting designs have a superior efficient-power density trade-off over traditional designs. These power converters can provide numerous lowvoltage outputs over a wide input voltage range with a very fast dynamic response, which are ideal for powering logic devices in the mobile and high-performance computing markets. Both design and fabrication considerations for power converters using this architecture are addressed. The results are demonstrated in a 2.4 W dc-dc converter implemented in a 180 nm CMOS IC process and co-packaged with its passive components for high-performance. The converter operates from an input voltage of 2.7 V to 5.5 V with an output voltage of /= 80% efficiency.by David Giuliano.Ph.D

Design exploration and measurement benchmark of integrated-circuits based on graphene field-effect-transistors : towards wireless nanotransceivers

This doctoral thesis approaches the design requirements for future high / ultra-high data rate (from 100 Mbps to 100 Gbps) nanotransceivers (nanoTRx) applied to wireless nanonetworks which imply short/ultra-short distance ranges (3 cm ¿ 3 m). It explores graphene field-effect-transistors (GFET), by simulation against measurement benchmarks, as a potential solution for implementing large-signal high-frequency circuits, by virtue of graphene¿s one-atom thickness and high carrier-mobility extraordinary properties. Finally, the thesis discusses the challenges faced by GFETs, such as zero-bandgap and high metal-graphene contact-resistance, to be able to propose improvements for achieving the initial proposed goals. Chemical-Vapour-Deposition (CVD) GFET fabrication is considered, which is very promising for large-scale manufacturing (CMOS process compatible), and for that fast-computing large-signal compact modeling for complex circuit design is analysed in depth and optimized, and consequently a set of diverse large-signal static and dynamic GFET circuits are simulated and benchmarked against available measurements assessing the accuracy of the proposed models and deriving scaling prospects. An optimization of the current-to-voltage (I-V) characteristic of a GFET compact model, based upon drift-diffusion carrier transport, is presented. The improved accuracy at the Dirac point extends the model usability for GFETs when scaling parameters such as voltage supply (Vdd), gate length (L), dielectric thickness (tox) and carrier mobility (¿) for large-signal design exploration in circuits. The model accuracy is demonstrated through parameters fitting to measurements taken from CVD GFETs fabricated in the University of Siegen and Technical University of Milan. The script has been written in a standard behavioural language (Verilog-A), and extensively run in a commercial analog circuit simulator (Cadence environment) demonstrating its robustness. Besides a simple capacitance-to-voltage model (C-V), a small-signal parasitic capacitance model fitted to dynamic measurements for self-aligned CVD GFETs available in the literature is added, enabling to forecast maximum-frequency-of-oscillation (fmax) trends for future scaling. A design-oriented characterization of complementary inverter circuits (INV) based on GFETs is presented as well. Our proposed compact model is benchmarked at the circuit level against another compact model based on a virtual-source approach. Furthermore, a benchmark between simulations and measurements of already fabricated CVD GFET INVs is performed, and performance trends when scaling are derived. The same process is repeated for a more complex circuit, namely GFET ring-oscillators (RO). The transient regime simulations yield performance metrics in terms of oscillation frequency (fosc) and dynamic voltage range (¿Vosc), and consequently, against these metrics, a comprehensive design space exploration covering as input design variables parameters as tox, L, and Vdd is carried out. Being aware of the lack of voltage amplification shown by existing GFETs, the design exploration of a cascode amplifier (CAS) targeted to increase voltage gain (Av) by decreasing its output conductance (go) is presented. GFET CAS are simulated to provide design guidelines, they are accordingly fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance (gm) and hence Av. Against these metrics, a quantitative comparison between CAS and GFETs is performed and conclusions are derived. Finally, conclusions on GFETs suitability for future nanoTRX are elaborated. The derived publications come from international collaborations with the Royal Institute of Technology (KTH) in Sweden from 2012 to 2014, and the University of Siegen in Germany from 2014 to 2016.Esta tesis doctoral trata de identificar los requisitos de diseño para nano-ransceptores (nanoTRx) con datos de alta velocidad (de 100 Mbps a 100 Gbps) aplicados a nano-redes inal ámbricas que implican rangos de alcance cortos u ultra-cortos (3 cm - 3 m ); explora FETs de grafeno (GFET), mediante simulaciones y mediciones, como una solución potencial para la implementación de circuitos de alta frecuencia de gran señal, gracias a las extraordinarias propiedades del grafeno como su espesor de un solo átomo y sus portadores de alta movilidad; y finalmente, se discuten los desafíos a los que se enfrentan los GFETs, como la falta de banda prohibida y la alta resistencia de contacto, para lograr proponer alternativas y poder alcanzar los objetivos iniciales propuestos. Las publicaciones derivadas provienen de Colaboraciones internacionales con el KTH en Suecia de 2012 a 2014, y la UniSiegen en Alemania de 2014 a 2016. Se introducen la técnica CVD como un proceso de fabricación de GFETs a gran escala, compatible con tecnología CMOS, muy prometedor; y el modelado compacto de gran señal y computación veloz para el diseño de circuitos complejos es optimizados y analizado en profundidad, Consecuentemente circuitos de gran señal (estáticos y dinámicos) basados en GFET son simulados y comparados con las mediciones disponibles para evaluar la precisi ón de los modelos propuestos y derivar prospecciones de escalado. Se propone una optimización de la característica corriente-voltaje (I-V) de un modelo compacto GFET, basado en el transporte de portadores difusi ón-deriva. La precisión mejorada en el punto de Dirac extiende la usabilidad del modelo para GFETs cuando se dimensionan parámetros para la exploración en diseños de circuitos de gran señal, tales como el voltaje de alimentación (Vdd), la longitud de puerta (L), el espesor diel éctrico (tOX) y la movilidad de portadores (U). La precisión del modelo se demuestra a través de parámetros que se ajustan a mediciones tomadas a partir de CVD GFETs fabricados en la UniSiegen y en el PoliMi. El programa se ha escrito en Verilog-A y se ejecuta extensivamente en un simulador de circuitos anal ógico comercial donde se demuestra su robustez. Además, se lleva a cabo la parametrización de un modelo capacidad-voltaje (C-V) que se ajusta a las mediciones de alta frecuencia de CVD GFETs disponibles en la literatura científica, lo que permite la predicción de la fMAX para el escalado de futuros GFETs. También se presenta una caracterización orientada al diseño de circuitos inversores complementarios (INV) basados en GFETs. Nuestro modelo compacto propuesto se compara a nivel de circuito con otro modelo compacto basado en fuentevirtual. A continuación, se lleva a cabo una comparación a nivel circuito entre las simulaciones y las medidas de INVs ya fabricados basados en CVD GFET, y se obtienen las tendencias de comportamiento al escalarlos. Se repite el mismo proceso para un circuito más complejo, los llamados osciladores-en-anillo GFET (RO). Las simulaciones basadas en transitorios producen métricas de rendimiento en términos de frecuencia de oscilación (fosc) y rango dinámico de voltaje (Vosc), por lo tanto, contra estas métricas, se lleva a cabo una exploración exhaustiva de diseño que abarca Parámetros de variables de diseño como tOX, L y Vdd. Al ser conscientes de la falta de amplificación de voltaje mostrada por los GFETs existentes, se presenta la exploración de diseño de un amplificador cascodo (CAS) diseñado para incrementar la amplificación de voltaje (Av) disminuyendo su conductancia de salida (go). Los GFET CAS son simulados para proporcionar guías de diseño, luego fabricadas y finalmente medidas. Se proporcionan métricas de rendimiento en términos de go, gm, y consecuentemente Av. Frente a estas métricas, se realiza una comparación cuantitativa entre CAS y GFETs y se derivan las conclusiones. Finalmente, se elaboran las conclusiones sobre la idoneidad de los GFET para futuros nanoTR

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Composite power semiconductor switches for high-power applications

It is predicted that 80 % of the world’s electricity will flow through power electronic based converters by 2030, with a growing demand for renewable technolo gies and the highest levels of efficiency at every stage from generation to load. At the heart of a power electronic converter is the power semiconductor switch which is responsible for controlling and modulating the flow of power from the input to the output. The requirements for these power semiconductor switches are vast, and include: having an extremely low level of conduction and switching losses; being a low source of electromagnetic noise, and not being susceptible to external Electromagnetic Interference (EMI); and having a good level of ruggedness and reliability. These high-performance switches must also be economically viable and not have an unnecessarily large manufacturing related carbon footprint. This thesis investigates the switching performance of the two main semiconductor switches used in high-power applications — the well-established Silicon (Si)-Insulated-Gate Bipolar Transistor (IGBT) and the state-of-the-art Wide-Bandgap (WBG) Silicon-Carbide (SiC)-Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET). The SiC-MOSFET is ostensibly a better device than the Si-IGBT due to the lower level of losses, however the cost of the device is far greater and there are characteristics which can be troublesome, such as the high levels of oscillatory behaviour at the switching edges which can cause serious Electromagnetic Compatibility (EMC) issues. The operating mechanism of these devices, the materials which are used to make them, and their auxiliary components are critically analysed and discussed. This includes a head-to-head comparison of the two high-capacity devices in terms of their losses and switching characteristics. The design of a high-power Double-Pulse Test Rig (DPTR) and the associated high-bandwidth measurement platform is presented. This test rig is then extensively used throughout this thesis to experimentally characterise the switching performance of the aforementioned high-capacity power semiconductor devices. A hybrid switch concept — termed “The Diverter” — is investigated, with the motivation of achieving improved switching performance without the high-cost of a full SiC solution. This comprises a fully rated Si-IGBT as the main conduction device and a part-rated SiC-MOSFET which is used at the turn-off. The coordinated switching scheme for the Si/SiC-Diverter is experimentally examined to determine the required timings which yield the lowest turn-off loss and the lowest level of oscillatory behaviour and other EMI precursors. The thermal stress imposed on the part-rated SiC-MOSFET is considered in a junction temperature simulation and determined to be negligible. This concept is then analysed in a grid-tied converter simulation and compared to a fully rated SiC-MOSFET and Si-IGBT. A conduction assistance operating mode, which solely uses the part-rated SiC-MOSFET when within its rating, is also investigated. Results show that the Diverter achieves a significantly lower level of losses compared to a Si-IGBT and only marginally higher than a full SiC solution. This is achieved at a much lower cost than a full SiC solution and may also provide a better method of achieving high-current SiC switche

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

NASA Tech Briefs, September 1990

Topics covered include: New Product Ideas; NASA TU Services; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences; Life Sciences