Digital Controlled Multi-phase Buck Converter with Accurate Voltage and Current Control

abstract: A 4-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and digital current sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line based PWM generator, without affecting the phase synchronization timing sequence. In light load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The DC-DC converter achieves 93% peak efficiency for Vi = 2V and Vo = 1.6V.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter

Modern application processors (microprocessors and Digital Signal Processors) are power hungry and demand power management solutions that can withstand their frequent and high slew-rate load transients while regulating their supply in a tight voltage tolerance. Hysteretic converter has excellent transient response performance but its variable switching frequency causes concern for electromagnetic interference in noise sensitive applications. A new frequency stabilization scheme for hysteretic buck dc-dc converters is proposed in this thesis. The equivalent series resistance (ESR) of the output capacitor is regulated by a phase-locked loop (PLL) to stabilize the operating frequency of the converter. The proposed fixed frequency ESR-controlled converter achieves a fixed 2MHz switching frequency, with less than 1µs response time to a 500mA load step while limiting undershoot and overshoot on the output voltage to 50mV and 40mV respectively. The performance of the presented work shows that the ESR of the output capacitor of a Hysteretic Buck Converter can be controlled to stabilize the switching frequency of the Hysteretic DC-DC Converter

An Effect of Output Capacitor ESL on Hysteretic PLL Controlled Multiphase Buck Converter

This paper provides analysis of output capacitor effects to phase stability of a hysteretic mode controlled buck converter. The hysteretic control method is a simple and fast control technique for switched-mode converters, but the hysteresis control is not oscillator referenced. It results in difficulty to achieve stable switching phase and frequency. In recent papers, the authors propose a use of phase locked loops (PLL) to permit interleaved multiphase operation where each voltage regulator (VR) module is coupled together via output node and leads to a strong loop interaction. In this work analysis of this interaction is studied by Matlab Simulink simulations and a new solution how to partially suppress this effect is given. The proposed method confirms the theoretical analysis

Variable Spurious Noise Mitigation Techniques in Hysteretic Buck Converters

This work proposes a current-mode hysteretic buck converter with a spur-free constant-cycle frequency-hopping controller that fully eliminates spurs from the switching noise spectrum irrespective of variations in the switching frequency and operating conditions. As a result, the need for frequency regulation loops to ensure non-varying switching frequency (i.e. fixed spurs location) in hysteretic controllers is eliminated. Moreover, compared to frequency regulation loops, the proposed converter offers the advantage of eliminating mixing and interference altogether due to its spur-free operation, and thus, it can be used to power, or to be integrated within noise-sensitive systems while benefiting from the superior dynamic performance of its hysteretic operation. The proposed converter uses dual-sided hysteretic band modulation to eliminate the inductor current imbalance that results from frequency hopping along with the output voltage transients and low-frequency noise floor peaking associated with it. Moreover, a feedforward adaptive hysteretic band controller is proposed to reduce variations in the switching frequency with the input voltage, and an all-digital soft-startup circuit is proposed to control the in-rush current without requiring any off-chip components. The converter is implemented in a 0.35-õm standard CMOS technology and it achieves 92% peak efficiency

Energy Storage as Enabling Technology for Smart Grid

Awareness about human impact on mighty climatic changes is radically changing our concept of energy. The thoughtless use of energy slowly leaves our habits and good use of energy is certain the way of a better future. CO2 emission reduction and carbon fossil fuel limitation are the main targets of governmental actions: this is possible thanks to technology improvement as efficient generation from renewable sources and good management of the electricity network. In recent years distributed generation, also of small size, grew up causing new management problems, indeed production from renewable energy sources (RES) is intermittent and unprogrammable. Energy storage systems can be a solution to these problems and pave the way to completely active users, grid parity and smart grid, moreover can be an useful tool to increase electricity access in rural areas. Research on energy storage is intrinsically a multidisciplinary field: storage types, power stages, technologies, topologies, weather, forecast, control algorithms, regulatory, safety and business cases to mention the most importants. In the present work is described the whole design of an energy storage system. First chapters are dedicated to a description of energy storage context, chapters 1 and 2; indeed, it is a matter of fact that in the last years, energy storage became more and more interesting from explicit mention as a tool against climatic changes to first options on the market. The general approach was the realization of a modular energy storage system for residential application, hardware and software design steps are deeply described in chapters 3 and 4. Simulations and tests on the prototype are reported in chapter 5. Finally conclusion and future works are given. At the end of the document some appendices are included to cover specific aspects touched during the work thesis

Time-based control techniques for integrated DC-DC conversion

Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrators while a delay line is used to perform voltage-to-time conversion and to sum time signals. A simple flip-flop generates a pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for a wide bandwidth error amplifier, pulse width modulator (PWM) in analog controllers or high-resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in a small area and with minimal power. First, a time-based single-phase buck converter is proposed and fabricated in a 180nm CMOS process, the prototype buck converter occupies an active area of 0.24mm^2, of which the controller occupies only 0.0375mm^2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V with 1.8V input voltage. With a 500mA step in the load current, the settling time is less than 3.5us and the measured reference tracking bandwidth is about 1MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2uA/MHz. Second, the techniques are extended to a high switching frequency multi-phase buck converter. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high-resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32mm^2, of which the controller occupies only 0.04mm^2. The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V from 1.8V input voltage. With a 400mA step in the load current, the settling time is less than 0.6us and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3uA/MHz. Finally, light load operation is discussed. The light load efficiency of a time-based buck converter is improved by adding proposed PFM control. At the same time, the proposed seamless transition techniques provide a freedom to change the control mode between PFM and PWM without deteriorating output voltage which allows for a system to manage its power efficiently. Fabricated in a 65nm CMOS, the prototype achieves 90% peak efficiency and > 80% efficiency over an ILOAD range of 2mA to 800mA. VO changes by less than 40mV during PWM to PFM transitions

Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators

Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time $(<0.1V/\mu s)$. This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities.Engineering and Applied Science

An Overview of Fully Integrated Switching Power Converters Based on Switched-Capacitor versus Inductive Approach and Their Advanced Control Aspects

This paper reviews and discusses the state of the art of integrated switched-capacitor and integrated inductive power converters and provides a perspective on progress towards the realization of efficient and fully integrated DC–DC power conversion. A comparative assessment has been presented to review the salient features in the utilization of transistor technology between the switched-capacitor and switched inductor converter-based approaches. First, applications that drive the need for integrated switching power converters are introduced, and further implementation issues to be addressed also are discussed. Second, different control and modulation strategies applied to integrated switched-capacitor (voltage conversion ratio control, duty cycle control, switching frequency modulation, Ron modulation, and series low drop out) and inductive converters (pulse width modulation and pulse frequency modulation) are then discussed. Finally, a complete set of integrated power converters are related in terms of their conditions and operation metrics, thereby allowing a categorization to provide the suitability of converter technologies

Energy-efficient wireline transceivers

Power-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques