13 research outputs found
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)
ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability
Acceleration for the many, not the few
Although specialized hardware promises orders of magnitude performance gains, their
uptake has been limited by how challenging it is to program them. Hardware accelerators
present challenges programmers are not used to, exposing details of the hardware that
are often hidden and requiring new programming styles to use them effectively.
Existing programming models often involve learning complex and hardware-specific
APIs, using Domain Specific Languages (DSLs), or programming in customized assembly languages. These programming models for hardware accelerators present a
significant challenge to uptake: a steep, unforgiving, and untransferable learning curve.
However, programming hardware accelerators using traditional programming models
presents a challenge: mapping code not written with hardware accelerators in mind to
accelerators with restricted behaviour.
This thesis presents these challenges in the context of the acceleration equation, and
it presents solutions to it in three different contexts: for regular expression accelerators,
for API-programmable accelerators (with Fourier Transforms as a key case-study) and
for heterogeneous coarse-grained reconfigurable arrays (CGRAs). This thesis shows
that automatically morphing software written in traditional manners to fit hardware
accelerators is possible with no programmer effort and that huge potential speedups are
available
Profile-driven parallelisation of sequential programs
Traditional parallelism detection in compilers is performed by means of static analysis
and more specifically data and control dependence analysis. The information that
is available at compile time, however, is inherently limited and therefore restricts the
parallelisation opportunities. Furthermore, applications written in C – which represent
the majority of today’s scientific, embedded and system software – utilise many lowlevel
features and an intricate programming style that forces the compiler to even more
conservative assumptions. Despite the numerous proposals to handle this uncertainty
at compile time using speculative optimisation and parallelisation, the software industry
still lacks any pragmatic approaches that extracts coarse-grain parallelism to exploit
the multiple processing units of modern commodity hardware.
This thesis introduces a novel approach for extracting and exploiting multiple forms
of coarse-grain parallelism from sequential applications written in C. We utilise profiling
information to overcome the limitations of static data and control-flow analysis
enabling more aggressive parallelisation. Profiling is performed using an instrumentation
scheme operating at the Intermediate Representation (Ir) level of the compiler.
In contrast to existing approaches that depend on low-level binary tools and debugging
information, Ir-profiling provides precise and direct correlation of profiling information
back to the Ir structures of the compiler. Additionally, our approach is orthogonal to
existing automatic parallelisation approaches and additional fine-grain parallelism may
be exploited.
We demonstrate the applicability and versatility of the proposed methodology using
two studies that target different forms of parallelism. First, we focus on the exploitation
of loop-level parallelism that is abundant in many scientific and embedded
applications. We evaluate our parallelisation strategy against the Nas and Spec Fp
benchmarks and two different multi-core platforms (a shared-memory Intel Xeon Smp
and a heterogeneous distributed-memory Ibm Cell blade). Empirical evaluation shows
that our approach not only yields significant improvements when compared with state-of-
the-art parallelising compilers, but comes close to and sometimes exceeds the performance
of manually parallelised codes. On average, our methodology achieves 96%
of the performance of the hand-tuned parallel benchmarks on the Intel Xeon platform,
and a significant speedup for the Cell platform. The second study, addresses
the problem of partially sequential loops, typically found in implementations of multimedia
codecs. We develop a more powerful whole-program representation based on the Program Dependence Graph (Pdg) that supports profiling, partitioning and codegeneration
for pipeline parallelism. In addition we demonstrate how this enhances
conventional pipeline parallelisation by incorporating support for multi-level loops and
pipeline stage replication in a uniform and automatic way. Experimental results using a
set of complex multimedia and stream processing benchmarks confirm the effectiveness
of the proposed methodology that yields speedups up to 4.7 on a eight-core Intel Xeon
machine
Architecture aware parallel programming in Glasgow parallel Haskell (GPH)
General purpose computing architectures are evolving quickly to become manycore
and hierarchical: i.e. a core can communicate more quickly locally than
globally. To be effective on such architectures, programming models must be
aware of the communications hierarchy. This thesis investigates a programming
model that aims to share the responsibility of task placement, load balance, thread
creation, and synchronisation between the application developer and the runtime
system.
The main contribution of this thesis is the development of four new architectureaware
constructs for Glasgow parallel Haskell that exploit information about task
size and aim to reduce communication for small tasks, preserve data locality, or to
distribute large units of work. We define a semantics for the constructs that specifies the sets of PEs that each construct identifies, and we check four properties
of the semantics using QuickCheck.
We report a preliminary investigation of architecture aware programming
models that abstract over the new constructs. In particular, we propose architecture
aware evaluation strategies and skeletons. We investigate three common
paradigms, such as data parallelism, divide-and-conquer and nested parallelism,
on hierarchical architectures with up to 224 cores. The results show that the
architecture-aware programming model consistently delivers better speedup and
scalability than existing constructs, together with a dramatic reduction in the
execution time variability.
We present a comparison of functional multicore technologies and it reports
some of the first ever multicore results for the Feedback Directed Implicit Parallelism
(FDIP) and the semi-explicit parallelism (GpH and Eden) languages. The
comparison reflects the growing maturity of the field by systematically evaluating
four parallel Haskell implementations on a common multicore architecture.
The comparison contrasts the programming effort each language requires with
the parallel performance delivered.
We investigate the minimum thread granularity required to achieve satisfactory
performance for three implementations parallel functional language on a
multicore platform. The results show that GHC-GUM requires a larger thread
granularity than Eden and GHC-SMP. The thread granularity rises as the number
of cores rises
Unconventional Applications of Compiler Analysis
Previously, compiler transformations have primarily focused on
minimizing program execution time. This thesis explores some examples
of applying compiler technology outside of its original scope.
Specifically, we apply compiler analysis to the field of software
maintenance and evolution by examining the use of global data
throughout the lifetimes of many open source projects. Also, we
investigate the effects of compiler optimizations on the power
consumption of small battery powered devices. Finally, in an area
closer to traditional compiler research we examine automatic program
parallelization in the form of thread-level speculation
The 1991 3rd NASA Symposium on VLSI Design
Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2
The Fifth NASA Symposium on VLSI Design
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design
Using MapReduce Streaming for Distributed Life Simulation on the Cloud
Distributed software simulations are indispensable in the study of large-scale life models but often require the use of technically complex lower-level distributed computing frameworks, such as MPI. We propose to overcome the complexity challenge by applying the emerging MapReduce (MR) model to distributed life simulations and by running such simulations on the cloud. Technically, we design optimized MR streaming algorithms for discrete and continuous versions of Conway’s life according to a general MR streaming pattern. We chose life because it is simple enough as a testbed for MR’s applicability to a-life simulations and general enough to make our results applicable to various lattice-based a-life models. We implement and empirically evaluate our algorithms’ performance on Amazon’s Elastic MR cloud. Our experiments demonstrate that a single MR optimization technique called strip partitioning can reduce the execution time of continuous life simulations by 64%. To the best of our knowledge, we are the first to propose and evaluate MR streaming algorithms for lattice-based simulations. Our algorithms can serve as prototypes in the development of novel MR simulation algorithms for large-scale lattice-based a-life models.https://digitalcommons.chapman.edu/scs_books/1014/thumbnail.jp