Hardware Precoding Demonstration in Multi-Beam UHTS Communications under Realistic Payload Characteristics

In this paper, we present a new hardware test-bed to demonstrate closed-loop precoded communications for interference mitigation in multi-beam ultra high throughput satellite systems under realistic payload and channel impairments. We build the test-bed to demonstrate a real-time channel aided precoded transmission under realistic conditions such as the power constraints and satellite-payload non-linearities. We develop a scalable architecture of an SDR platform with the DVB-S2X piloting. The SDR platform consists of two parts: analog-to-digital (ADC) and digital-to-analog (DAC) converters preceded by radio frequency (RF) front-end and Field-Programmable Gate Array (FPGA) backend. The former introduces realistic impairments in the transmission chain such as carrier frequency and phase misalignments, quantization noise of multichannel ADC and DAC and non-linearities of RF components. It allows evaluating the performance of the precoded transmission in a more realistic environment rather than using only numerical simulations. We benchmark the performance of the communication standard in realistic channel scenarios, evaluate received signal SNR, and measure the actual channel throughput using LDPC codes

End-to-end Precoding Validation over a Live GEO Satellite Forward Link

In this paper we demonstrate end-to-end precoded multi-user multiple-input single-output (MU-MISO) communications over a live GEO satellite link. Precoded communications enable full frequency reuse (FFR) schemes in satellite communications (SATCOM) to achieve broader service availability and higher spectrum efficiency than with the conventional four-color (4CR) and two-color (2CR) reuse approaches. In this scope, we develop an over-the-air test-bed for end-to-end precoding validations. We use an actual multi-beam satellite to transmit and receive precoded signals using the DVB-S2X standard based gateway and user terminals. The developed system is capable of end-to-end real-time communications over the satellite link including channel measurements and precompensation. It is shown, that by successfully canceling inter-user interference in the actual satellite FFR link precoding brings gains in terms of enhanced SINR and increased system goodput.Comment: Submitted to IEEE Access Journa

Hardware Demonstration of Precoded Communications in Multi-Beam UHTS Systems

In this paper, we present a hardware test-bed to demonstrate closed-loop precoded communications for interference mitigation in the forward link of the multi-beam ultra-high throughput satellite systems. The hardware demonstrator is a full-chain closed-loop communication system with a multi-beam DVB-S2X compliant gateway, a satellite payload and MIMO channel emulator and a set of DVB-S2X user terminals with real-time CSI estimation and feedback. We experimentally show the feasibility of Precoding implementation in satellite communications based on the superframe structure DVB-S2X standard. Using the test-bed we have a possibility to run real-time precoded DVB-S2X communication and benchmark its performance under realistic environment. The hardware demonstrator is suitable to perform realistic benchmarks of Block- and Symbol-level Precoding techniques for multicast and unicast user scheduling scenarios

FPGA Acceleration for Computationally Efficient Symbol-Level Precoding in Multi-User Multi-Antenna Communication Systems

In this paper, we demonstrate an FPGA accelerated design of the computationally efficient Symbol-Level Precoding (SLP) for high-throughput communication systems. The SLP technique recalculates optimal beam-forming vectors by solving a non-negative least squares (NNLS) problem per every set of transmitted symbols. It exploits the advantages of constructive inter-user interference to minimize the total transmitted power and increase service availability. The benefits of using SLP come with a substantially increased computational load at a gateway. The FPGA design enables the SLP technique to perform in realtime operation mode and provide a high symbol throughput for multiple receive terminals. We define the SLP technique in a closed-form algorithmic expression and translate it to Hardware Description Language (HDL) and build an optimized HDL core for an FPGA. We evaluate the FPGA resource occupation, which is required for high throughput multiple-input-multiple-output (MIMO) systems with sizeable dimensions. We describe the algorithmic code, the I/O ports mapping and the functional behavior of the HDL core. We deploy the IP core to an actual FPGA unit and benchmark the energy efficiency performance of SLP. The synthetic tests demonstrate a fair energy efficiency improvement of the proposed closed-form algorithm, also compared to the best results obtained through MATLAB numerical simulations

Fast Memory-Based Processing in Software-Defined Radios

Negli ultimi anni le Software Defined Radio sono state un argomento di ricerca di primo piano nell'ambito dei sistemi di trasmissione radio. Molti e variegati paradigmi implementativi sono stati concepiti e proposti, con soluzioni capaci di spaziare da sistemi basati su Field Programmable Gate Array (FPGA) a implementazioni ottenute mediante un singolo General Purpose Processor (GPP) passando per dispositivi caratterizzati dalla presenza computazionalmente preponderante di un Digital Signal Processor (DSP) o da architetture miste. Tali soluzioni rappresentano punti di equilibrio diversi dell'inevitabile compromesso tra flessibilità e capacità computazionale del sistema di trasmissione implementato, comprimendo in qualche modo l'aspirazione ad un sistema radio universale propria del concetto originario dell'SDR. A questo riguardo, le soluzioni SDR basate su GPP rappresentano il modello implementativo maggiormente desiderabile in quanto costituiscono l'alternativa più flessibile ed economica tra tutte le tipologie di SDR. Ciò nonostante, la scarsa capacità computazionale ha sempre limitato l'adozione di questi sistemi in scenari produttivi di vasta scala. Se convenientemente applicati entro il contesto di sviluppo SDR, concetti classici noti in informatica sotto la denominazione collettiva di space/time trade-off possono essere di enorme aiuto quando si cerchi di mitigare un simile problema. Traendo ispirazione da detti concetti, nonché estendendoli ed applicandoli all'abito dell'SDR, questa tesi sviluppa e presenta una tecnica di programmazione specifica per software radio chiamata Memory Acceleration (MA) che, mediante un uso estensivo delle risorse di memoria disponibili a bordo di un tipico sistema di calcolo general purpose, può fornire alle SDR convenzionali basate su GPP fattori di accelerazione sostanziali (circa un ordine di grandezza) senza ridurne la peculiare flessibilità. Alcune rilevanti implementazioni di sistemi SDR capaci di lavorare in tempo reale su processori GPP consumer-grade realizzate in tecnica MA sono descritte in dettaglio entro questo lavoro di tesi e fornite come prova della reale efficacia del concetto proposto

Enhancing mobile services with DVB-S2X superframing

DVB-S2X is the cornerstone for satellite communication standards forming the state of the art of broadband satellite waveforms. In this paper, we propose new application scenarios and advanced techniques, including a reference design implementing superframing, predistortion, a robust synchronization chain, and a plug-and-play channel interleaver. We demonstrate by means of software simulations and hardware tests that the DVB-S2X can be a common technology enabler for land-mobile, aeronautical, and maritime satellite scenarios in addition to the more traditional VSAT scenario, even in very challenging conditions (eg, very low signal-to-noise ratio)