Computer architecture for efficient algorithmic executions in real-time systems: New technology for avionics systems and advanced space vehicles

Improvements and advances in the development of computer architecture now provide innovative technology for the recasting of traditional sequential solutions into high-performance, low-cost, parallel system to increase system performance. Research conducted in development of specialized computer architecture for the algorithmic execution of an avionics system, guidance and control problem in real time is described. A comprehensive treatment of both the hardware and software structures of a customized computer which performs real-time computation of guidance commands with updated estimates of target motion and time-to-go is presented. An optimal, real-time allocation algorithm was developed which maps the algorithmic tasks onto the processing elements. This allocation is based on the critical path analysis. The final stage is the design and development of the hardware structures suitable for the efficient execution of the allocated task graph. The processing element is designed for rapid execution of the allocated tasks. Fault tolerance is a key feature of the overall architecture. Parallel numerical integration techniques, tasks definitions, and allocation algorithms are discussed. The parallel implementation is analytically verified and the experimental results are presented. The design of the data-driven computer architecture, customized for the execution of the particular algorithm, is discussed

Dynamic Systolization for Developing Multiprocessor Supercomputers

A dynamic network approach is introduced for developing reconfigurable, systolic arrays or wavefront processors; This allows one to design very powerful and flexible processors to be used in a general-purpose, reconfigurable, and fault-tolerant, multiprocessor computer system. The concepts of macro-dataflow and multitasking can be integrated to handle variable-resolution granularities in computationally intensive algorithms. A multiprocessor architecture, Remps, is proposed based on these design methodologies. The Remps architecture is generalized from the Cedar, HEP, Cray X- MP, Trac, NYU ultracomputer, S-l, Pumps, Chip, and SAM projects. Our goal is to provide a multiprocessor research model for developing design methodologies, multiprocessing and multitasking supports, dynamic systolic/wavefront array processors, interconnection networks, reconfiguration techniques, and performance analysis tools. These system design and operational techniques should be useful to those who are developing or evaluating multiprocessor supercomputers

Systolic Ring: A new approach for dynamical reconfigurable architectures

Motivated by the growing requirements in performances which the current architectures will not soon be able any more to face, this article presents a new approach for the design of digital signal processing IC. Having expressed the problem, we underline the respective limitations of the classic structures such as processors and FPGA, and we present hybrid architecture of these two families presenting a level of unprecedented performances. We detail the principles of dynamical reconfiguration on which our architecture is based, then present comparative results on a well known multimedia applications algorithm (DCT algorithm). Finally we describe the results obtained by fast prototyping and the current works concerning the problems of compilation targeting of our architecture.Motivé par les exigences grandissantes en puissance de traitement auxquelles les architectures actuelles ne seront bientôt plus à même de faire face, cet article présente une nouvelle approche pour la réalisation de circuits à caractère traitement du signal. Après avoir énoncé le problème, nous soulignerons les limitations respectives des structures classiques telles que processeurs et FPGA, et présenterons une architecture hybride de ces deux familles affichant un niveau de performances sans précédent. Nous détaillerons les principes de reconfiguration dynamique sur lesquels notre architecture est basée, puis présenterons des résultats comparatifs sur un algorithme caractéristique des applications multimédia (DCT). Enfin nous exposerons les résultats obtenus par prototypage de la structure ainsi que les travaux en cours concernant les problématiques de compilation ciblant notre architecture

The Dataflow Computational Model And Its Evolution

Το υπολογιστικό μοντέλο dataflow είναι ένα εναλλακτικό του von-Neumann. Τα κυριότερα χαρακτηριστικά του είναι ο ασύγχρονος προγραμματισμός εργασιών και το ότι επιτρέπει μαζική παραλληλία. Αυτή η πτυχιακή είναι μία μελέτη αυτού του μοντέλου, καθώς και μερικών υβριδικών μοντέλων, που βρίσκονται ανάμεσα στο αρχικό μοντέλο dataflow και στο von-Neumann. Τέλος, υπάρχουν αναφορές σε μερικές αρχές του dataflow, οι οποίες έχουν υιοθετηθεί σε συμβατικές μηχανές, γλώσσες προγραμματισμού και συστήματα κατανεμημένων υπολογισμών.The dataflow computational model is an alternative to the von-Neumann model. Its most significant aspects are, that it is based on asynchronous instructions scheduling and exposes massive parallelism. This thesis is a review of the dataflow computational model, as well as of some hybrid models, which lie between the pure dataflow and the von Neumann model. Additionally, there are some references to dataflow principles, that are or are being adopted by conventional machines, programming languages and distributed computing systems

'n Ondersoek na die geskiktheid van 'n datavloeiverwerker as 'n herstruktureerbare spesiale verwerker

Thesis (MEng.) -- Stellenbosch Universiteit, 1984.AFRIKAANSE OPSOMMING: Hierdie tesis behels 'n ondersoek na die geskiktheid van 'n datavloei-verwerker om as 'n herstruktureerbare spesiale verwerker te dien. Die werking van 'n datavloei-verwerkermodel word aan die hand van datavloeikonsepte verduidelik. Die tekortkominge van die model, naamlik die gebrek aan datastruktuur-hanterings, toevoer/afvoer en hertoelatingsmeganismes wor-d uitgelig en moontlike oplos~ings word gege•• 'n Semodifiseerde datavloei-model, wat beide struktuurhantering en toevoer/afvoermeganismes insluit, word voorgestel. Hertoelating word met behulp van 'n datapakketbenamingsmetode bewerkstellig. Om die programmeerbaarheid en die herstruktureerbaarheid van die model te ondersoek, is besluit om 'n datavloei-verwerker te simuleer. Die model is met behulp van die hoevlaktaal PASCAL, en bedryfstelselroepe op die VAX 11/780 rekenaar gesimuleer. ParallelIe verwerkingskonsepte in beide programmatuur en argitektuur word gedemonstreer

Micro data flow processor design

Computer has evolved rapidly during the past several decades in terms of its implementation technology; it's architecture, however, has not changed dramatically since the von Neumann computer(control flow) model emerged in the 1940s. One main reason is that the performance for this kind of computers was able to satisfy the requirement of most users. Another reason maybe that the engineers who designed them are more familiar with this model. However, recent solutions to the problem of parallelizing sequential nature instructions on a von Neumann machine complicate both the compiler and the controller design. Therefore, another computer model, namely the data flow model, has regained attention since this model of computation exposes parallelism inherent in the program naturally. In terms of implementation methodology, we currently use synchronous sequential logic, which is clock controlled for synchronization within circuits. This design philosophy becomes hard to follow due to the occurrence of clock skew as the clock frequency goes higher and higher. One way to eliminate these clock related problems is to use the self-timed(asynchronous) implementation methodology. It features advantages such as free of clock-skew, low power consumption, composibility and so forth. Since data flow(data driven) computation model provides the execution of instructions asynchronously, it is natural to implement a data flow processor using self-timed circuits. In this thesis, micro pipelines, one of the self-timed implementation methodology, is used to implement a preliminary version of general purpose static data flow processor. Some interesting observations will be addressed in this thesis. An example program of general difference recursive equation is given to test the correctness and performance of this processor. We hope to gain more insight on how to design and implement self-timed systems in the future