A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF) radio-frequency identification (RFID) transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C

Process and Temperature Compensation of CMOS Ring Oscillators

In order to compensate RO's process, temperature and voltage variations (PVT) several CMOS effects have been studied such as VT sensing and Zero Temperature Coefficient (ZTC). A single-ended RO topology was analysed taking into consideration theoretical studies, PVT behavior and sensitivity to control and supply voltage. The techniques used to obtain these characterizations helped to obtain, organize and classify data in a efficient and scalable manner. The modified false-position method was implemented to characterize the RO PVT behavior efficiently for a given target oscillation frequency, allowing to explore different RO's and specific transistor influence. For classification a coefficient of determination, pronounced R squared, was implemented allowing to know the goodness of fit of a line for instance RO's control voltage, and find straight, parallel and evenly spaced lines. Analysis of the supply and control voltage sensitivity to a variation was made allowing good error prediction and a clear way for correctly knowing how to compensate variations. An ideal topology was developed for matching two sets of those lines with similar features on different circuits, containing gain, offset and coefficient of temperature.The final topology includes two Bandgap voltage references, a simple VT extractor, a Differential Amplifier and a single-end RO

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma

High performance readout circuits and devices for Lorentz force resonant CMOS-MEMS magnetic sensors

In the last decades, sensing capabilities of martphones have greatly improved since the early mobile phones of the 90’s. Moreover, wearables and the automotive industry require increasing electronics and sensing sophistication. In such echnological advance, Micro Electro Mechanical Systems (MEMS) have played an important role as accelerometers and gyroscopes were the first sensors based on MEMS technology massively introduced in the market. In contrast, it still does not exist a commercial MEMS-based compass, even though Lorentz force MEMS magnetometers were first proposed in the late 90’s. Currently, Lorentz force MEMS magnetometers have been under the spotlight as they can offer an integrated solution to nowadays sensing power. As a consequence, great advances have been achieved, but various bottlenecks limit the introduction of Lorentz force MEMS compasses in the market. First, current MEMS magnetometers require high current consumption and high biasing voltages to achieve good sensitivities. Moreover, even though devices with excellent performance and sophistication are found in the literature, there is still a lack of research on the readout electronic circuits, specially in the digital signal processing, and closed loop control. Second, most research outcomes rely on custom MEMS fabrication rocesses to manufacture the devices. This is the same approach followed in current commercial MEMS, but it requires different fabrication processes for the electronics and the MEMS. As a consequence, manufacturing cost is high and sensor performance is affected by the MEMS-electronics interface parasitics. This dissertation presents potential solutions to these issues in order to pave the road to the commercialization of Lorentz force MEMS compasses. First, a complete closed loop, digitally controlled readout system is proposed. The readout circuitry, implemented with off-the-shelf commercial components, and the digital control, on an FPGA, are proposed as a proof of concept of the feasibility, and potential benefits, of such architecture. The proposed system has a measured noise of 550 nT / vHz while the MEMS is biased with 300 µA rms and V = 1 V . Second, various CMOS-MEMS magnetometers have been designed using the BEOL part of the TSMC and SMIC 180 nm standard CMOS processes, and wet and vapor etched. The devices measurement and characterisation is used to analyse the benefits and drawbacks of each design as well as releasing process. Doing so, a high volume manufacturing viability can be performed. Yield values as high as 86% have been obtained for one device manufactured in a SMIC 180 nm full wafer run, having a sensitivity of 2.82 fA/µT · mA and quality factor Q = 7.29 at ambient pressure. While a device manufactured in TSMC 180 nm has Q = 634.5 and a sensitivity of 20.26 fA/µT ·mA at 1 mbar and V = 1 V. Finally, an integrated circuit has been designed that contains all the critical blocks to perform the MEMS signal readout. The MEMS and the electronics have been manufactured using the same die area and standard TSMC 180 nm process in order to reduce parasitics and improve noise and current consumption. Simulations show that a resolution of 8.23 µT /mA for V = 1 V and BW = 10 Hz can be achieved with the designed device.En les últimes dècades, tenint en compte els primers telèfons mòbils dels anys 90, les capacitats de sensat dels telèfons intel·ligents han millorat notablement. A més, la indústria automobilística i de wearables necessiten cada cop més sofisticació en el sensat. Els Micro Electro Mechanical Systems (MEMS) han tingut un paper molt important en aquest avenç tecnològic, ja que acceleròmetres i giroscopis varen ser els primers sensors basats en la tecnologia MEMS en ser introduïts massivament al mercat. En canvi, encara no existeix en la indústria una brúixola electrònica basada en la tecnologia MEMS, tot i que els magnetòmetres MEMS varen ser proposats per primera vegada a finals dels anys 90. Actualment, els magnetòmetres MEMS basats en la força de Lorentz són el centre d'atenció donat que poden oferir una solució integrada a les capacitats de sensat actuals. Com a conseqüència, s'han aconseguit grans avenços encara que existeixen diversos colls d'ampolla que encara limiten la introducció al mercat de brúixoles electròniques MEMS basades en la força de Lorentz. Per una banda, els agnetòmetres MEMS actuals necessiten un consum de corrent i un voltatge de polarització elevats per aconseguir una bona sensibilitat. A més, tot i que a la literatura hi podem trobar dispositius amb rendiments i sofisticació excel·lents, encara existeix una manca de recerca en el circuit de condicionament, especialment de processat digital i control del llaç. Per altra banda, moltes publicacions depenen de processos de fabricació de MEMS fets a mida per fabricar els dispositius. Aquesta és la mateixa aproximació que s'utilitza actualment en la indústria dels MEMS, però té l'inconvenient que requereix processos de fabricació diferents pels MEMS i l’electrònica. Per tant, el cost de fabricació és alt i el rendiment del sensor queda afectat pels paràsits en la interfície entre els MEMS i l'electrònica. Aquesta tesi presenta solucions potencials a aquests problemes amb l'objectiu d'aplanar el camí a la comercialització de brúixoles electròniques MEMS basades en la força de Lorentz. En primer lloc, es proposa un circuit de condicionament complet en llaç tancat controlat digitalment. Aquest s'ha implementat amb components comercials, mentre que el control digital del llaç s'ha implementat en una FPGA, tot com una prova de concepte de la viabilitat i beneficis potencials que representa l'arquitectura proposada. El sistema presenta un soroll de 550 nT / vHz quan el MEMS està polaritzat amb 300 µArms i V = 1 V . En segon lloc, s'han dissenyat varis magnetòmetres CMOS-MEMS utilitzant la part BEOL dels processos CMOS estàndard de TSMC i SMIC 180 nm, que després s'han alliberat amb líquid i gas. La mesura i caracterització dels dispositius s’ha utilitzat per analitzar els beneficis i inconvenients de cada disseny i procés d’alliberament. D'aquesta manera, s'ha pogut realitzar un anàlisi de la viabilitat de la seva fabricació en massa. S'han obtingut valors de yield de fins al 86% per un dispositiu fabricat amb SMIC 180 nm en una oblia completa, amb una sensibilitat de 2.82 fA/µT · mA i un factor de qualitat Q = 7.29 a pressió ambient. Per altra banda, el dispositiu fabricat amb TSMC 180 nm presenta una Q = 634.5 i una sensibilitat de 20.26 fA/µT · mA a 1 mbar amb V = 1 V. Finalment, s'ha dissenyat un circuit integrat que conté tots els blocs per a realitzar el condicionament de senyal del MEMS. El MEMS i l'electrònica s'han fabricat en el mateix dau amb el procés estàndard de TSMC 180 nm per tal de reduir paràsits i millorar el soroll i el consum de corrent. Les simulacions mostren una resolució de 8.23 µT /mA amb V = 1 V i BW = 10 Hz pel dispositiu dissenyat