38 research outputs found
Direct Conversion RF Front-End Implementation for Ultra-Wideband (UWB) and GSM/WCDMA Dual-Band Applications in Silicon-Based Technologies
This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range.
For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.Ph.D.Committee Chair: Dr. Laskar, Joy; Committee Member: Dr. Cressler, John; Committee Member: Dr. Kohl, Paul; Committee Member: Dr. Papapolymerou, John; Committee Member: Dr. Scott, Waymon
System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits
This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system
CMOS Integrated Circuit Design for Ultra-Wideband Transmitters and Receivers
Ultra-wideband technology (UWB) has received tremendous attention since the
FCC license release in 2002, which expedited the research and development of UWB
technologies on consumer products. The applications of UWB range from ground
penetrating radar, distance sensor, through wall radar to high speed, short distance
communications. The CMOS integrated circuit is an attractive, low cost approach for
implementing UWB technology. The improving cut-off frequency of the transistor in
CMOS process makes the CMOS circuit capable of handling signal at multi-giga herz.
However, some design challenges still remain to be solved. Unlike regular narrow band
signal, the UWB signal is discrete pulse instead of continuous wave (CW), which results
in the occupancy of wide frequency range. This demands that UWB front-end circuits
deliver both time domain and frequency domain signal processing over broad bandwidth.
Witnessing these technique challenges, this dissertation aims at designing novel, high
performance components for UWB signal generation, down-conversion, as well as
accurate timing control using low cost CMOS technology. We proposed, designed and fabricated a carrier based UWB transmitter to
facilitate the discrete feature of the UWB signal. The transmitter employs novel twostage
-switching to generate carrier based UWB signal. The structure not only minimizes
the current consumption but also eliminates the use of a UWB power amplifier. The
fabricated transmitter is capable of delivering tunable UWB signal over the complete
3.1GHz -10.6GHz UWB band. By applying the similar two-stage switching approach,
we were able to implement a novel switched-LNA based UWB sampling receiver frontend.
The proposed front-end has significantly lower power consumption compared to
previously published design while keep relatively high gain and low noise at the same
time. The designed sampling mixer shows unprecedented performance of 9-12dB voltage
conversion gain, 16-25dB noise figure, and power consumption of only 21.6mW(with
buffer) and 11.7mW(without buffer) across dc to 3.5GHz with 100M-Hz sampling
frequency.
The implementation of a precise delay generator is also presented in the
dissertation. It relies on an external reference clock to provide accurate timing against
process, supply voltage and temperature variation through a negative feedback loop. The
delay generator prototype has been verified having digital programmability and tunable
delay step resolution. The relative delay shift from desired value is limited to within
0.2%
A 3.1-4.8GHz IR-UWB All-Digital Pulse Generator in 0.13-um CMOS Technology for WBAN Systems
Analog, Digital & RF Circuit DesignImpulse Radio Ultra-WideBand (IR-UWB) systems have drawn growing attention for wireless sensor networks such as Wireless Personal Area Network (WPAN) and Wireless Body Area Network (WBAN) systems ever since the Federal Communications Commission (FCC) released the spectrum between 3.1 and 10.6GHz for unlicensed use in 2002. The restriction on transmitted power spectral density in this band is equal to the noise emission limit of household digital electronics. This band is also shared with several existing service, therefore in-band interference is expected and presents a challenge to UWB system design.
UWB devices as secondary spectrum users must also detect and avoid (DAA) other licensed users from the cognitive radio???s point of view. For the DAA requirement, it is more effective to deploy signal with variable center frequency and a minimum 10dB bandwidth of 500MHz than a signal covering the entire UWB spectrum range with fixed center frequency.
A key requirement of the applications using IR-UWB signal is ultra-low power consumption for longer battery life. Also, cost reduction is highly desirable. Recently, digital IR-UWB pulse generation is studied more than analog approach due to its lower power consumption.
An all-digital pulse generator in a standard 0.13-um CMOS technology for communication systems using Impulse Radio Ultra-WideBand (IR-UWB) signal is presented. A delay line-based architecture utilizing only static logic gates and leading lower power consumption for pulse generation is proposed in this thesis. By using of all-digital architecture, energy is consumed by CV2 switching losses and sub-threshold leakage currents, without RF oscillator or analog bias currents. The center frequency and the fixed bandwidth of 500MHz of the output signal can be digitally controlled to cover three channels in low band of UWB spectrum. Delay based Binary Shift Keying (DB-BPSK) and Pulse Position Modulation (PPM) schemes are exploited at the same time to modulate the transmitted signals with further improvement in spectrum characteristics. The total energy consumption is 48pJ/pulse at 1.2V supply voltage, which is well suitable for WBAN systems.ope
Ultra-Wideband CMOS Transceiver Front-End for Bio-Medical Radar Sensing
Since the Federal Communication Commission released the unlicensed 3.1-10.6 GHz frequency band for commercial use in early 2002, the ultra wideband (UWB) has developed from an emerging technology into a mainstream research area. The UWB technology, which utilizes wide spectrum, opens a new era of possibility for practical applications in radar sensing, one of which is the human vital sign monitoring.
The aim of this thesis is to study and research the possibility of a new generation humanrespiration monitoring sensor using UWB radar technology and to develop a new prototype of UWB radar sensor for system-on-chip solutions in CMOS technology. In this thesis, a lowpower Gaussian impulse UWB mono-static radar transceiver architecture is presented. The UWB Gaussian pulse transmitter and receiver are implemented and fabricated using 90nm CMOS technology. Since the energy of low order Gaussian pulse is mostly condensed at
lower frequency, in order to transmit the pulse in a very efficient way, higher order Gaussian derivative pulses are desired as the baseband signal. This motivates the advancement of the design into UWB high-order pulse transmitter. Both the Gaussian impulse UWB transmitter and Gaussian higher-order impulse UWB transmitter take the low-power and high-speed advantage of digital circuit to generate different waveforms. The measurement results are analyzed and discussed.
This thesis also presents a low-power UWB mono-static radar transceiver architecture exploiting the full benefit of UWB bandwidth in radar sensing applications. The transceiver includes a full UWB band transmitter, an UWB receiver front-end, and an on-chip diplexer.
The non-coherent UWB transmitter generates pulse modulated baseband signals at different carrier frequencies within the designated 3-10 GHz band using a digitally controlled pulse generator. The test shows the proposed radar transceiver can detect the human respiration pattern within 50 cm distance.
The applications of this UWB radar sensing solution in commercialized standard CMOS technology include constant breathing pattern monitoring for gated radiation therapy, realtime monitoring of patients, and any other breathing monitoring. The research paves the way to wireless technology integration with health care and bio-sensor network
SiGe-based broadband and high suppression frequency doubler ICs for wireless communications
制度:新 ; 報告番号:甲3419号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574
Design of High-Bandwidth and High-Linearity Input Buffers for ADCs
Nowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized
with a higher voltage supply than that of the core voltage of the technology, mainly for
linearity purposes. This, in turn, makes it mandatory to have more than one voltage
source to supply a single chip in addition to having devices capable of handling higher
voltages.
This work explores the possibility of having IBs supplied with the technology’s core
voltage to standardize all of the devices and reducing the different voltage supply sources
and/or voltage regulators needed for operating the front-end drivers of the Analog to
Digital Converters (ADCs).
A new input buffer architecture will be presented and compared to some prior input
buffer implementations in the same conditions. This new architecture presents good
linearity and bandwidth results and can be used for input buffers with the added benefit
of not needing higher voltages nor special devices.
This new architecture is based off an existing one with another feedback loop to
improved high-frequency peaking and linearity issues. This architecture achieves better
results in bandwidth, a SNDR of 58 dB with and output voltage of 600 mV peak-to-peak
differential. Furthermore, this buffer achieves a better efficiency linearity-wise when
comparing to other buffers in the same conditions
Design of a 3.1-4.8 GHZ RF front-end for an ultra wideband receiver
IEEE 802.15 High Rate Alternative PHY task group (TG3a) is working to define
a protocol for Wireless Personal Area Networks (WPANs) which makes it possible to
attain data rates of greater than 110Mbps. Ultra Wideband (UWB) technology utilizing
frequency band of 3.168 GHz 10.6 GHz is an emerging solution to this with data rates
of 110, 200 and 480 Mbps. Initially, UWB mode I devices using only 3.168 GHz 4.752
GHz have been proposed.
Low Noise Amplifier (LNA) and I-Q mixers are key components constituting the
RF front-end. Performance of these blocks is very critical to the overall performance of
the receiver. In general, main considerations for the LNA are low noise, 50 broadband
input matching, high gain with maximum flatness and good linearity. For the mixers, it
is essential to attain low flicker noise performance coupled with good conversion gain.
Proposed LNA architecture is a derivative of inductive source degenerated topology.
Broadband matching at the LNA output is achieved using LC band-pass filter. To obtain
high gain with maximum flatness, an LC band-pass filter is used at its output. Proposed
LNA achieved a gain of 15dB, noise figure of less than 2.6dB and IIP3 of more than
-7dBm.
Mixer is a modified version of double balanced Gilbert cell topology where both
I and Q channel mixers are merged together. Frequency response of each sub-band is
matched by using an additional inductor, which further improves the noise figure and
conversion gain. Current bleeding scheme is used to further reduce the low frequency
noise. Mixer achieves average conversion gain of 14.5dB, IIP3 more than 6dBm and
Double Side Band (DSB) noise figure less than 9dB. Maximum variation in conversion
gain is desired to be less than 1dB. Both LNA and mixers are designed to be fabricated
in TSMC 0.18µm CMOS technology