Nowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized
with a higher voltage supply than that of the core voltage of the technology, mainly for
linearity purposes. This, in turn, makes it mandatory to have more than one voltage
source to supply a single chip in addition to having devices capable of handling higher
voltages.
This work explores the possibility of having IBs supplied with the technology’s core
voltage to standardize all of the devices and reducing the different voltage supply sources
and/or voltage regulators needed for operating the front-end drivers of the Analog to
Digital Converters (ADCs).
A new input buffer architecture will be presented and compared to some prior input
buffer implementations in the same conditions. This new architecture presents good
linearity and bandwidth results and can be used for input buffers with the added benefit
of not needing higher voltages nor special devices.
This new architecture is based off an existing one with another feedback loop to
improved high-frequency peaking and linearity issues. This architecture achieves better
results in bandwidth, a SNDR of 58 dB with and output voltage of 600 mV peak-to-peak
differential. Furthermore, this buffer achieves a better efficiency linearity-wise when
comparing to other buffers in the same conditions
