A 3 Gb/s optical detector in standard CMOS for 850 nm optical communication

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations

A 19-channel d.c. SQUID magnetometer system for brain research

A 19-channel d.c. SQUID magnetometer system for neuromagnetic investigations is under constuction. The first-order gradiometers for sensing the signal are placed in a hexagonal configuration. D.c. SQUIDs based on niobium/aluminium technology have been developed, leading to a field sensitivity of about 5 fT/ Hz. SQUID read-out is realized with a resonant transformer circuit at 100 kHz. The multichannel control and detection electronics are compactly built

Software Defined DCF77 Receiver

This paper shows the solution of time stamp software defined receiver integration into low cost com-mercial devices. The receiver is based on a general pur-pose processor and its analog to digital converter. The amplified signal from a narrow-band antenna is connected to the converter and no complicated filtration has to be used. All signal processing is digitally provided by the processor. During signal reception, the processor stays available for its main tasks and signal processing con-sumes only a small part of its computational power

The UT 19-channel DC SQUID based neuromagnetometer

A l9-channel DC SQUID based neuromagnetometer is under construction at the University of Twente (UT). Except for the cryostat all elements of the system are developed at the UT. It comprises 19 wire-wound first-order gradiometers in a hexagonal configuration. The gradiometers are connected to planar DC SQUIDS fabricated with a Nb/Al, AlOx/Nb technology. For this connection we developed a method to bond a Nb wire to a Nb thin-film. The SQUIDs are placed in compartmentalised Nb modules. Further, external feedback is incorporated in order to eliminate cross talk between the gradiometers. The electronics basically consist of a phase-locked loop operating with a modulation frequency of 100 kHz. Between SQUID and preamplifier a small transformer is used to limit the noise contribution of the preamplifier. In the paper the overall system is described, and special attention is paid to the SQUID module (bonding, compartments, external-feedback setup, output transformer)

System architecture study of an orbital GPS user terminal

The generic RF and applications processing requirements for a GPS orbital navigator are considered. A line of demarcation between dedicated analog hardware, and software/processor implementation, maximizing the latter is discussed. A modular approach to R/PA design which permits several varieties of receiver to be constructed from basic components is described. It is a basic conclusion that software signal processing of the output of the baseband correlator is the best choice of transition from analog to digital signal processing. High performance sets requiring multiple channels are developed from a generic design by replicating the RF processing segment, and modifying the applications software to provide enhanced state propagation and estimation

The PreAmplifier ShAper for the ALICE TPC-Detector

In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, self-adaptive bias network, two second-order bridged-T filters, two non-inverting level shifters and a start-up circuit. The circuit is optimized for a detector capacitance of 18-25 pF. For an input capacitance of 25 pF, the PASA features a conversion gain of 12.74 mV/fC, a peaking time of 160 ns, a FWHM of 190 ns, a power consumption of 11.65 mW/ch and an equivalent noise charge of 244e + 17e/pF. The circuit recovers smoothly to the baseline in about 600 ns. An integral non-linearity of 0.19% with an output swing of about 2.1 V is also achieved. The total area of the chip is 18 mm$^2$ and is implemented in AMS's C35B3C1 0.35 micron CMOS technology. Detailed characterization test were performed on about 48000 PASA circuits before mounting them on the ALICE TPC front-end cards. After more than two years of operation of the ALICE TPC with p-p and Pb-Pb collisions, the PASA has demonstrated to fulfill all requirements

Saturation in cascaded optical amplifier free-space optical communication systems

The performance of a free-space optical (FSO) communication system in a turbulent atmosphere employing an optical amplifier (OA) cascade to extend reach is investigated. Analysis of both single and cascaded OA FSO communication links is given and the implications of using both adaptive (to channel state) and non-adaptive decision threshold schemes are analysed. The benefits of amplifier saturation, for example in the form of effective scintillation reduction when a non-adaptive decision threshold scheme is utilised at the receiver for different atmospheric turbulence regimes, are presented. Monte Carlo simulation techniques are used to model the probability distributions of the optical signal power, noise and the average bit error rate due to scintillation for the cascade. The performance of an adaptive decision threshold is superior to a non-adaptive decision threshold for both saturated and fixed gain preamplified receivers and the ability of a saturated gain OA to suppress scintillation is only meaningful for system performance when a non-adaptive decision threshold is used at the receiver. An OA cascade can be successfully used to extend reach in FSO communication systems and specific system implementations are presented. The optimal cascade scheme with a non-adaptive receiver would use frequent low gain saturated amplification

Mobile Phone Power Amplifier Linearity and Efficiency Enhancement Using Digital Predistortion

The new generation mobile communication systems using spectrum efficient linear modulation schemes (QPSK,8PSK,QAM)need linear power amplifiers in the transmission path to have good ACPR and EVM values. Linearization methods can be used to increase the linearity of the power amplifiers (PA).However,it is not reasonable o use complicated,power consuming and high cost systems. This paper presents a digital predistortion implementation for WCDMA signals using an FPGA (Field Programmable Gate Array)as DSP and investigates the application of this system in handsets.The method applied requires minimum change in the conventional transmitter path configuration but considerable PAE improvement can be achieved

Preamplifier-shaper prototype for the Fast Transition Detector of the Compressed Baryonic Matter (CBM) experiment at FAIR

In this work a preamplifier-shaper prototype for the Fast Transition Detector of the Compressed BaryonicMatter (CBM) experiment at FAIR fabricated using a 0.35 μm CMOS technology will be presented. The ASIC integrates 16 identical Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, two bridged-T filters, Common-Mode FeedBack (CMFB) network and two non-inverting level shifting stages. The circuit is optimized for a detector capacitance Cd of (5-10)pF. Measurement results confirm the noise of 330 e− + 12 e−/pF obtained in simulations for a pulse with a Full Width Half Maximum (FWHM) of 71 ns. The circuit recovers to the baseline within 200 ns. The conversion gain is 12.64 mV/fC. An integral nonlinearity of 0.7% is also achieved. The maximum output swing is 2 V. The power consumption is 16 mW/channel where the main contributors are the input transistor and the level shifting stage with 5.3 mW and 6.6 mW, respectively. The total area of the chip is 12 mm2. Although the circuit was designed for a positive input charge it has in addition the ability of handling negative current pulses of about 85% of the typical charge of 165 fC without any degradation of the signal. The chip was submitted for manufacturing in AMS’s C35B4M3 0.35 micron CMOS technology in October 2005. This circuit has been successfully used in the CBM test-beam at GSI Darmstadt in February 2006