A review on mitigation technologies of low frequency current ripple injected into fuel cell and a case study

© 2020 Hydrogen Energy Publications LLC This paper reviews the state-of-the-art of mitigation technologies of low frequency current ripple (LFCR) injected into fuel cell (FC). Although there are their own merits and demerits, the optimized LFCR control techniques and topology structures are characterized in many aspects like performance, durability, reliability and lifetime of FC. Three mains topologies and mitigation methods of LFCR have been investigated based on the literature review, which are the passive compensation methods, active compensation methods, and passive and active hybrid compensation methods. Some rules based tables are set to evaluate the LFCR against the topologies, control strategies, current ripple, application and advantages/limitations. Moreover, the mitigation control strategies are compared side by side with their specific applications in FC system. To select and implement them, this review can provide a reference and basis for the researchers in related fields. Finally, a case study in an uninterruptible power supply application is conducted

An investigation of harmonic correction techniques using active filtering

This thesis presents an investigation of techniques used to mitigate the undesirable effects of harmonics in power systems. The first part of this research develops an effective and useful comparison of alternative AC-DC converter topologies. In particular, a full evaluation of the circuit first proposed by Enjeti (known here as the Texas circuit) with a capacitively smoothed output voltage is made, specifically for operation as a 'clean power' supply interface for a variable speed drive (VSD). This mode of operation has not previously been reported in research literature. Simulation and experimental results verify the performance of the circuit and demonstrate that it draws a current with low harmonic content, but the circuit has a number of problems. This part of the research concludes that the six-switch rectifier is the most viable circuit for operation as a supply interface for a VSD due to its bidirectional power flow capability and its excellent versatility of performance. The second part of this research exploits the versatility of the six-switch rectifier and develops the current control strategy for operation of the circuit as a sinusoidal frontend and as a shunt active filter. It is found that the 'traditional' current control method suffers a significant drop in performance when the switching frequency is constrained to 2kHz due to high power levels. The major development in this thesis was an advanced current control strategy, where additional rotating frames of reference are introduced, thereby converting previously oscillatory current values to d.c. values. This is demonstrated to result in vastly improved immunity to disturbances such as supply distortion and a greatly improved steady state performance. In addition, the new controller requires no additional circuitry (apart from current transducers on the load current) and can be applied to an existing sinusoidal front end. Simulation results confirm the operation of the controller with the circuit operating as both a shunt active filter and as a sinusoidal front end. The new controller has been implemented on an experimental rig exhibiting the features of a high power inverter, i.e. low switching frequency and significant device turn-on and turn-off times, and the results confirm the superior performance of the new current controller

An investigation of harmonic correction techniques using active filtering

This thesis presents an investigation of techniques used to mitigate the undesirable effects of harmonics in power systems. The first part of this research develops an effective and useful comparison of alternative AC-DC converter topologies. In particular, a full evaluation of the circuit first proposed by Enjeti (known here as the Texas circuit) with a capacitively smoothed output voltage is made, specifically for operation as a 'clean power' supply interface for a variable speed drive (VSD). This mode of operation has not previously been reported in research literature. Simulation and experimental results verify the performance of the circuit and demonstrate that it draws a current with low harmonic content, but the circuit has a number of problems. This part of the research concludes that the six-switch rectifier is the most viable circuit for operation as a supply interface for a VSD due to its bidirectional power flow capability and its excellent versatility of performance. The second part of this research exploits the versatility of the six-switch rectifier and develops the current control strategy for operation of the circuit as a sinusoidal frontend and as a shunt active filter. It is found that the 'traditional' current control method suffers a significant drop in performance when the switching frequency is constrained to 2kHz due to high power levels. The major development in this thesis was an advanced current control strategy, where additional rotating frames of reference are introduced, thereby converting previously oscillatory current values to d.c. values. This is demonstrated to result in vastly improved immunity to disturbances such as supply distortion and a greatly improved steady state performance. In addition, the new controller requires no additional circuitry (apart from current transducers on the load current) and can be applied to an existing sinusoidal front end. Simulation results confirm the operation of the controller with the circuit operating as both a shunt active filter and as a sinusoidal front end. The new controller has been implemented on an experimental rig exhibiting the features of a high power inverter, i.e. low switching frequency and significant device turn-on and turn-off times, and the results confirm the superior performance of the new current controller

Low Power Filtering Techniques for Wideband and Wireless Applications

This dissertation presents design and implementation of continuous time analog filters for two specific applications: wideband analog systems such as disk drive channel and low-power wireless applications. Specific focus has been techniques that reduce the power requirements of the overall system either through improvement in architecture or efficiency of the analog building blocks. The first problem that this dissertation addresses is the implementation of wideband filters with high equalization gain. An efficient architecture that realizes equalization zeros by combining available transfer functions associated with a biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with 24dB boost is designed using the proposed architecture. The prototype fabricated in standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though at the cost of much larger area. Secondly, a complementary current mirror based building block is proposed, which pushes the limits imposed by conventional transconductors on the powerefficiency of Gm-C filters. Signal processing through complementary devices provides good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly 7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in 1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter realization occupies a relatively small area and is well suited for integration in deep submicron technologies. Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter is designed for a ten bit continuous time sigma delta ADC architecture developed specifically for fine-line CMOS technologies. Inverter based amplification and a common mode feedback for such amplifiers are discussed. The filter consumes 5mW of power and occupies an area of 0.07 mm2

Clock Generation Design for Continuous-Time Sigma-Delta Analog-To-Digital Converter in Communication Systems

Software defined radio, a highly digitized wireless receiver, has drawn huge attention in modern communication system because it can not only benefit from the advanced technologies but also exploit large digital calibration of digital signal processing (DSP) to optimize the performance of receivers. Continuous-time (CT) bandpass sigma-delta (ΣΔ) modulator, used as an RF-to-digital converter, has been regarded as a potential solution for software defined ratio. The demand to support multiple standards motivates the development of a broadband CT bandpass ΣΔ which can cover the most commercial spectrum of 1GHz to 4GHz in a modern communication system. Clock generation, a major building block in radio frequency (RF) integrated circuits (ICs), usually uses a phase-locked loop (PLL) to provide the required clock frequency to modulate/demodulate the informative signals. This work explores the design of clock generation in RF ICs. First, a 2-16 GHz frequency synthesizer is proposed to provide the sampling clocks for a programmable continuous-time bandpass sigma-delta (ΣΔ) modulator in a software radio receiver system. In the frequency synthesizer, a single-sideband mixer combines feed-forward and regenerative mixing techniques to achieve the wide frequency range. Furthermore, to optimize the excess loop delay in the wideband system, a phase-tunable clock distribution network and a clock-controlled quantizer are proposed. Also, the false locking of regenerative mixing is solved by controlling the self-oscillation frequency of the CML divider. The proposed frequency synthesizer performs excellent jitter performance and efficient power consumption. Phase noise and quadrature phase accuracy are the common tradeoff in a quadrature voltage-controlled oscillator. A larger coupling ratio is preferred to obtain good phase accuracy but suffer phase noise performance. To address these fundamental trade-offs, a phasor-based analysis is used to explain bi-modal oscillation and compute the quadrature phase errors given by inevitable mismatches of components. Also, the ISF is used to estimate the noise contribution of each major noise source. A CSD QVCO is first proposed to eliminate the undesired bi-modal oscillation and enhance the quadrature phase accuracy. The second work presents a DCC QVCO. The sophisticated dynamic current-clipping coupling network reduces injecting noise into LC tank at most vulnerable timings (zero crossing points). Hence, it allows the use of strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed DCC QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1MHz offset from a 5GHz carrier. The QVCO consumes 4.2mW with a 1-V power supply, resulting in an outstanding Figure of Merit (FoM) of 189 dBc/Hz. Frequency divider is one of the most power hungry building blocks in a PLL-based frequency synthesizer. The complementary injection-locked frequency divider is proposed to be a low-power solution. With the complimentary injection schemes, the dividers can realize both even and odd division modulus, performing a more than 100% locking range to overcome the PVT variation. The proposed dividers feature excellent phase noise. They can be used for multiple-phase generation, programmable phase-switching frequency dividers, and phase-skewing circuits

Energy Shaping Control for Stabilization of Interconnected Voltage Source Converters in Weakly-Connected AC Microgrid Systems

With the ubiquitous installations of renewable energy resources such as solar and wind, for decentralized power applications across the United States, microgrids are being viewed as an avenue for achieving this goal. Various independent system operators and regional transmission operators such as Southwest Power Pool (SPP), Midcontinent System Operator (MISO), PJM Interconnection and Electric Reliability Council of Texas (ERCOT) manage the transmission and generation systems that host the distributed energy resources (DERs). Voltage source converters typically interconnect the DERs to the utility system and used in High voltage dc (HVDC) systems for transmitting power throughout the United States. A microgrid configuration is built at the 13.8kV 4.75MVA National Center for Reliable Energy Transmission (NCREPT) testing facility for performing grid-connected and islanded operation of interconnected voltage source converters. The interconnected voltage source converters consist of a variable voltage variable frequency (VVVF) drive, which powers a regenerative (REGEN) load bench acting as a distributed energy resource emulator. Due to the weak-grid interface in islanded mode testing, a voltage instability occurs on the VVVF dc link voltage causing the system to collapse. This dissertation presents a new stability theorem for stabilizing interconnected voltage source converters in microgrid systems with weak-grid interfaces. The new stability theorem is derived using the concepts of Dirac composition in Port-Hamiltonian systems, passivity in physical systems, eigenvalue analysis and robust analysis based on the edge theorem for parametric uncertainty. The novel stability theorem aims to prove that all members of the classes of voltage source converter-based microgrid systems can be stabilized using an energy-shaping control methodology. The proposed theorems and stability analysis justifies the development of the Modified Interconnection and Damping Assignment Passivity-Based Control (Modified IDA-PBC) method to be utilized in stabilizing the microgrid configuration at NCREPT for mitigating system instabilities. The system is simulated in MATLAB/SimulinkTM using the Simpower toolbox to observe the system’s performance of the designed controller in comparison to the decoupled proportional intergral controller. The simulation results verify that the Modified-IDA-PBC is a viable option for dc bus voltage control of interconnected voltage source converters in microgrid systems

Convertidor de frente activo usando en generador hidroeléctrico con velocidad ajustable

Descargue el texto completo en el repositorio institucional de la Norwegian University of Science and Technology: http://hdl.handle.net/11250/2624265En esta tesis se ha estudiado los controladores de corriente y voltaje del convertidor de red tipo LCL, también llamado Convertidor de Frente Activo o Active Front End Converter (AFE), con más énfasis en la correcta sintonización de los controladores para un funcionamiento estable, considerando que el sistema de control debe ser adaptable a las variaciones en la frecuencia del sistema causadas por perturbaciones en la red. El análisis de estabilidad se ha realizado mediante los diagramas de Nyquist y los diagramas de Bode. Se ha propuesto un procedimiento de ajuste para obtener una solución robusta y estable. Como parte del procedimiento de ajuste, se ha desarrollado y propuesto un método de compensación de retardo, considerando las propiedades particulares que los controladores resonantes con y sin amortiguamiento, así como con y sin compensación de retardo, tienen en el plano z. La idoneidad de la metodología propuesta se ha evaluado mediante simulaciones

Baseband analog circuits in deep-submicron cmos technologies targeted for mobile multimedia

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling