Digital Solutions for Analog Shortcomings in Delta-Sigma Analog-to-Digital Converters

Portable, high power efficiency communication devices is a growing market in the semiconductor industry. Analog-to-digital converters (ADC) are key interface that are used to digitize the sensed information. Recently, digital techniques have been proposed to improve analog building block power efficiency in sub-micron technologies. This research focuses on mixed signal approaches to improve the power efficiency of the noise shaping ADCs and mitigate analog inaccuracies such as non-linearity and mismatch. First, a novel continuous-time filtering delta-sigma ADC is proposed to save power and area. Digital techniques have been proposed to make the architecture more robust to out-of-band unwanted signals. A prototype was fabricated in a 65 nm CMOS technology achieving an SNDR of 72.4 dB operating at 250 MHz sampling frequency over 7 MHz bandwidth, with a power consumption of 16.3 mW. Next, A novel digital circuitry is proposed to improve the tolerance of a discrete-time delta sigma ADC to mismatch and enhance the resolution of an ADC in the presence of mismatch. A custom IC was fabricated in a 65 nm CMOS technology consuming 40.4 μA from a 1 V supply. It achieves 76.18 dB SNDR operating at 1.2 MHz sampling frequency and 25 kHz signal bandwidth

Multi-Stage Noise-Shaping Continuous-Time Sigma-Delta Modulator

The design of a single-loop continuous-time ∑∆ modulator (CT∑∆M) with high resolution, wide bandwidth, and low power consumption is very challenging. The multi-stage noise-shaping (MASH) CT∑∆M architecture is identified as an advancement to the single-loop CT∑∆M architecture in order to satisfy the ever stringent requirements of next generation wireless systems. However, it suffers from the problems of quantization noise leakage and non-ideal interstage interfacing which hinder its widespread adoption. To solve these issues, this dissertation proposes a MASH CT∑∆M with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise cancellation filter (NCF). The prototype core modulator architecture is a cascade of two single-loop second- order CT∑∆M stages, each of which consists of an integrator-based active-RC loop filter, current-steering feedback digital-to-analog converters, and a four-bit flash quantizer. On-chip RC time constant calibration circuits and high gain multi-stage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to (i) synthesize a fourth-order noise transfer function with DC zeros, (ii) simplify the design of NCF, and (iii) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40 nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise and distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43.0 mW of power consumption (P). It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as FOM = SNDR + 10 log10(BW/P), is 165.1 dB

Design of a Moderate-Resolution Dual-Slope ADC using Noise-Shaping Techniques and a Double Speed Quantizer

Being the slowest Analog-to-Digital Converter, the Dual-Slope quantizer is often used in sigma-delta ADC or SAR converter architectures, and in measurement instruments, due to its high accuracy. Despite the utility of the quantizer and the existent techniques to increase the accuracy and the conversion speed, the usability of this converter is still very limited by the its slow conversion rate. The main interest of the Dual-Slope Quantizer lies in the high accuracy from the quantization technique used. To convert the input value, the value is integrated in the charge phase, by an integrator circuit, to be quantized, in the discharging phase using a digital block. Other benefits of the Dual-Slope Quantizers are the small size when implemented in a system on a chip (SOC) and the low power consumption. By reducing the the conversion time of this ADC, while maintaining the high accuracy it will be possible to increase the converters utility, such as in IoT devices, or even mobile devices, benefiting all from the high accuracy and low power consumption of this circuit. Nowadays, many techniques are being used in the Dual-Slope converters, such as, the addition of bi-directional capabilities, to increase the conversion speed, the addition of an half LSB compensation, to increase the accuracy, and the use of Noise-Shaping capabilities originated from the quantization error from each discharge phase. All of this techniques are presented and used in this research. For the proposed solution, a Double-Speed Quantizer composed of two additional comparators will be added to grant the conversion speed increase, which will increase the power consumption and will lead to a redesigning of the digital block to receive more inputs. As result the conversion speed will double in comparison to the existent 4 bit dual slope quantizer, being needed 8 clock cycles to quantize a input value, instead of 16

ダイナミック・アナログ回路を用いる高精度AD変換器の設計技術に関する研究

東京都市大学2018年度（平成30年

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm 2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW

Design and automation techniques for hIgh-performance mixed-signal circuits

In the era of ubiquitous sensing environment, the modern electronic system expands our perception of the outside world. Analog/mixed-signal circuit has played a critical role to bridge the physical and digital worlds. The boom of Internet-of-Things (IoT), bio-sensing, and digital camera calls for versatile high-performance mixed-signal circuits and the corresponding automated design methodology. However, high-performance analog circuits are area or power hungry. Moreover, the design cost is prohibitively expensive. To address these challenges, this dissertation explores solutions from both the design and automation techniques. Analog-to-digital converter (ADC) is an important subset of analog/mixed-signal circuits. Continuous time Delta-Sigma modulator (CTDSM) is a popular design choice for high-speed and high-resolution designs. CTDSMs feature a higher power efficiency than their discrete-time (DT) counterpart. The first work presents a high-speed 4th-order DSM featuring the CT-DT hybridization and an efficient excess-loop-delay (ELD) compensation technique in the charge domain. Compared to prior high-order CTDSMs, the proposed hybrid DSM achieves 4th-order noise shaping with single operational trans-conductance amplifier (OTA). Minimized number of OTAs reduces power and enhances stability. On top of that, an efficient ELD compensation technique is implemented by utilizing the inherent capacitor digital-to-analog converter (CDAC) of SAR. Fabricated in 40 nm CMOS, the prototype ADC achieved a peak Schreier Figure-of-Merits (FoM) of 176.1 dB, marking 4 dB improvement over prior arts. The second project explores the techniques to reduce the area consumption of high-resolution CTDSMs. The performance of existing high-resolution CTDSMs is limited by the feedback DAC. The stringent non-linearity requirement leads to the large area of DAC. To address this limitation, a low-complexity hardware-based 2nd-order dynamic-element-matching (DEM) is proposed. The partial sorter applied to the DEM minimizes the hardware cost. Moreover, feedforward path assisted loop filter adapts the highly-linear integrator design to the low power supply voltage. With these techniques combined, the prototype shows a feasible design pattern to achieve compact-area, high-resolution design at advanced technology nodes. A prototype fabricated in 40 nm CMOS measured 95dB SNDR, occupying only 0.37 mm² area. After the exploration of pushing the ADC performance boundary, this dissertation also demonstrates the automated design methodology. The design cost of high-performance mixed-signal circuit grows exponentially with the technology scaling. Existing analog automation techniques cannot handle practical circuit design constraints (e.g. robustness against variations). The third work presents RobustAnalog, a variation-aware analog circuit optimization via multi-task reinforcement learning (RL) and task-space pruning. RobustAnalog is mainly designed to tackle the process-voltage-temperature (PVT) robustness in the analog design. Correlations between similar variations are modeled and conflicts between distinct variations are mitigated. With task pruning, a small-sized proxy training task set is formed. The pruning reduces the queries to the full task set. Compared with the popular blackbox optimization methods, RobustAnalog significantly reduces the simulation cost. Therefore, RobustAnalog shows the staggering progress towards analog automation techniques that can be applied to real silicon conditions.Electrical and Computer Engineerin