Carbon footprint of 3D-printed bone tissue engineering scaffolds: an life cycle assessment study

The bone tissue engineering scaffolds is one of the methods for repairing bone defects caused by various factors. According to modern tissue engineering technology, three-dimensional (3D) printing technology for bone tissue engineering provides a temporary basis for the creation of biological replacements. Through the generated 3D bone tissue engineering scaffolds from previous studies, the assessment to evaluate the environmental impact has shown less attention in research. Therefore, this paper is aimed to propose the Model of life cycle assessment (LCA) for 3D bone tissue engineering scaffolds of 3D gel-printing technology and presented the analysis technique of LCA from cradle-to-gate for assessing the environmental impacts of carbon footprint. Acrylamide (C3H5NO), citric acid (C6H8O7), N,N-Dimethylaminopropyl acrylamide (C8H16N2O), deionized water (H2O), and 2-Hydroxyethyl acrylate (C5H8O3) was selected as the material resources. Meanwhile, the 3D gel-printing technology was used as the manufacturing processes in the system boundary. The analysis is based on the LCA Model through the application of GaBi software. The environmental impact was assessed in the 3D gel-printing technology and it was obtained that the system shows the environmental impact of global warming potential (GWP). All of the emissions contributed to GWP have been identified such as emissions to air, freshwater, seawater, and industrial soil. The aggregation of GWP result in the stage of manufacturing process for input and output data contributed 47.6% and 32.5% respectively. Hence, the data analysis of the results is expected to use for improving the performance at the material and manufacturing process of the product life cycle

Low-power high-speed ADC design techniques in scaled CMOS process

The power consumption of a single-channel successive approximation register (SAR) analog-to-digital (ADC) tends to linearly increase with its sampling rate (f[subscript s]), when f[subscript s] is small. However, when f[subscript s] passes a certain point for a given technology node, the ADC power P increases at much higher rate and the normalized power efficiency (P/f[subscript s]) starts to degrade rapidly. To enhance the conversion speed of SAR ADC, while maintaining a good power efficiency, this thesis presents speed-enhancing techniques for SAR ADC in nano-scale CMOS technologies. First chapter presents a 2b/cycle hybrid SAR architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, 2b/cycle conversion technique can boost the f[subscript s] of the ADC without any additional DAC arrays. High-speed ADCs can boost the conversion speed not only by increasing the f[subscript s] of a single-channel ADC, but also by time-interleaving multiple ADC sub-channels running at a lower rate. For an N-channel time-interleaved (TI) SAR ADC operating at f[subscript s], each sub-SAR channel only needs to operate at f[subscript s]=N. Therefore, each sub-SAR can operate in the linear power versus speed region, leading to a significant power saving compared to a single-channel ADC running at the same sampling rate. Despite of its power efficiency, TI-ADC suffers from mismatches among sub-ADC channels, including gain, offset, and timing mismatches. Among them, timing skew is one of the most difficult errors to calibrate as it is nontrivial to extract and its induced error depends on both the frequency and the amplitude of the input signal. Second chapter of this thesis presents a TI-SAR with a fast variance-based timing-skew calibration technique. It uses a single-comparator based window detector (WD) to calibrate the timing skew. The WD suppresses variance estimation errors and allow precise variance estimation from a significantly small number of samples. It has low-hardware cost and orders of magnitude faster convergence speed compared to prior variance-based timing-skew calibration technique. The last chapter presents another TI-SAR with mean absolute deviation (MAD) based timing-skew calibration technique. In addition to all the advantages presented with the fast variance-based timing-skew calibration technique, the proposed technique further reduces the digital computation power by 50% by eliminating the squaring operations, which are essential in variance-based calibration techniqueElectrical and Computer Engineerin

Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology

Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors, environmental and biomedical monitoring devices. This study presents a low power Flash ADC designed in nanometer complementary metal-oxide semiconductors (CMOS) technology. Time analysis on the output delay of the comparators helps to generate one more bit. The proposed technique reduced the power consumption and chip area substantially in comparison to the previous state-of-the-art work. The proposed ADC was developed in TSMC 65nm CMOS technology. The offset cancellation technique was embedded in the proposed comparator to decrement the static offset of the comparator. Moreover, one more bit was generated without using extra comparators. The proposed ADC achieved 4.1 bits ENOB at input Nyquist frequency. The simulated differential and integral non-linearity static tests were equal to +0.26/-0.17 and +0.22/-0.15, respectively. The ADC consumed 7.7 mW at 1 GHz sampling frequency, achieving 415 fJ/Convstep Figure of Merit (FoM)

Design techniques for low-power SAR ADCs in nano-scale CMOS technologies

This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparator’s power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparator’s offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Electrical and Computer Engineerin

A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology

A novice advanced architecture of 8-bit analog todigital converter is introduced and analyzed in this work. Thestructure of proposed ADC is based on the sub-ranging ADCarchitecture in which a 4-bit resolution flash-ADC is utilized. Theproposed ADC architecture is designed by employing a comparatorwhich is equipped with common mode current feedback andgain boosting technique (CMFD-GB) and a residue amplifier. Theproposed 8 bits ADC structure can achieve the speed of 140 megasamplesper second. The proposed ADC architecture is designedat a resolution of 8 bits at 10 MHz sampling frequency. DNL andINL values of the proposed design are -0.94/1.22 and -1.19/1.19respectively. The ADC design dissipates a power of 1.24 mWwith the conversion speed of 0.98 ns. The magnitude of SFDRand SNR from the simulations at Nyquist input is 39.77 and 35.62decibel respectively. Simulations are performed on a SPICE basedtool in 90 nm CMOS technology. The comparison shows betterperformance for the proposed ADC design in comparison toother ADC architectures regarding speed, resolution and powerconsumption

Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies

This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’ speed is limited by the number of bits of resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed up the conversion process, we introduce a radix-3 SAR ADC which can compute 1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently hardware controlled radix-3 SAR ADC. We had to use two comparators per cycle due to ADC architecture and we proposed a simple calibration scheme for the comparators. Also, as the architecture of the DAC array is completely different from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up with an algorithm for calibration of capacitors of the DAC. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs. To improve the comparator’s power efficiency, an efficient and low cost calibration technique has been introduced. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR). To improve the DAC switching energy, we introduced a radix-3/radix-2 based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR ADC and these two single ended DACs can be used as one differential DAC for radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix- 2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2 search to reduce the DAC capacitor size and hence, to reduce switching power. It can reduce the total number of unit capacitors by four times. Our proposed hybrid SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR ADCs. Also, to utilize technology scaling, we used the minimum capacitor size allowed by thermal noise limitations. To achieve high resolution, we introduced calibration algorithm for the DAC array. As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional radix-2 SAR ADC because of simultaneous use of two comparators. In the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB bits. So, the resolution required for radix-3 comparators are much larger than the LSB value of 10-bit ADC. By implementing calibration of comparators, we can use low power, high input referred offset and high speed comparators for radix-3 search. Radix-2 search will be used for rest of the bits and the resolution of the radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search. Also, we introduced clock gating for comparators. So, radix-3 comparators will not toggle during radix-2 search and the radix-2 comparators will be inactive during radix-3 search. By using the aforementioned techniques, the overall comparator power is definitely less than a radix-3 SAR ADC and comparable to a conventional radix-2 SAR ADC. A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed technique is designed and fabricated in 40nm CMOS technology. It achieves an SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a Walden figure of merit of 21.5 fJ/conv-step.Electrical and Computer Engineerin

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUAA low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively