Entwurfsregeln für supraleitende Analog-Digital-Wandler

This Thesis is a contribution for dimensioning aspects of circuits designs in superconductor electronics. Mainly superconductor comparators inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were investigated in terms of speed and sensitivity. The influence of the thermal noise on the decision process of the comparators represent in so called gray zone, which is analysed in this thesis. Thereby, different relations between design parameters were derived. A circuit model of the Josephson comparator was verified by experiments. Concepts of superconductor analog-to-digital converters, which are based on above called comparators, were investigated in detail. From the comparator design rules, new rules for AD-converters were derived. Because of the reduced switching energy, the signal to noise ratio (SNR) of the circuits is affected and therefore the reliability of the decision-process is affected. For special applications with very demanding requirements in terms of the speed and accuracy superconductor analog-to-digital converters offer an excellent performance. This thesis provides relations between different design paramenters and shows resulting trade-offs, This method is transparent and easy to transfer to other circuit topologies. As a main result, a highly predictive tool for dimensioning of superconducing ADC's is proved.Die vorliegende Dissertationsschrift liefert einen Beitrag zu Dimensionierungsaspekten des Schaltungsentwurfs in der supraleitender Elektronik. Dazu werden supraleitende Komparatoren, d. h. Josephson-Komparator und QOJS-Komparator bezüglich der Geschwindigkeit und der Empfindlichkeit untersucht. Der Einfluss des thermischen Rauschens auf den Entscheidungsprozess der Komparatoren repräsentiert die so genannte Grauzone. Sie wird in der Arbeit als wichtige Kennzahl ausführlich analysiert. Daraus werden verschiedene Parameterabhängigkeiten dargestellt. Eine Modellierung eines Josephson-Komparator wurde experimentell bestätigt. Darauf aufbauend werden Konzepte von supraleitenden Analog-Digital-Wandlern in der Arbeit untersucht und daraus Entwurfsregeln abgeleitet. Durch die Reduzierung der Schaltenegie wird das Signal-Rausch-Verhältnis (SNR) der Schaltungen und damit die Zuverlässigkeit von Entscheidungsprozessen und Schaltvorgängen beeinflusst. Für Spezialanwendungen mit sehr hohen Anforderungen bezüglich der Geschwindigkeit oder Genauigkeit bieten supraleitende AD-Wandler ausgezeichnete Leistungsmerkmale an. Die Arbeit liefert konkrete Zusammenhänge zwischen den unterschiedlichen Entwurfsparametern und zeigt mögliche Kompromisse auf. Die Methoden sind transparent dargestellt und lassen sich leicht auf andere Schaltungstopologien übertragen. Im Ergebnis wird ein Werkzeug zur objektiven Dimensionierung von supraleitenden AD-Wandlern bereitgestellt

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Energy Efficiency in Communications and Networks

The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe

Software model with verification of the imaging chamber in microwave tomography

Микроталасна томографија је метода за снимање објекта путем микроталаса. Након мерења објекта системом антена у комори решава се инверзни проблем нумеричком симулацијом и оптимизацијом. У овом раду се решава проблем верности моделовања антенског система у симулацији. Избегавањем апроксимација у моделовању антенског система, добија се вернији софтверски модел. Ради постизавања тог циља  жичана квадратна спирална антена је одабрана за коришћење у комори за снимање. Употреба предложене антене у микроталасној томографији је новитет. Реализован је софтверски симулациони модел коморе са предложеном антеном.  У симулацијама је извршено поређење са другим антенама често коришћеним у литератури за дату сврху. Израђен је прототип коморе са предложеним антенама. Извршена су мерења и поређења са предложеним моделом, како би се потврдила веродостојсност модела.Mikrotalasna tomografija je metoda za snimanje objekta putem mikrotalasa. Nakon merenja objekta sistemom antena u komori rešava se inverzni problem numeričkom simulacijom i optimizacijom. U ovom radu se rešava problem vernosti modelovanja antenskog sistema u simulaciji. Izbegavanjem aproksimacija u modelovanju antenskog sistema, dobija se verniji softverski model. Radi postizavanja tog cilja  žičana kvadratna spiralna antena je odabrana za korišćenje u komori za snimanje. Upotreba predložene antene u mikrotalasnoj tomografiji je novitet. Realizovan je softverski simulacioni model komore sa predloženom antenom.  U simulacijama je izvršeno poređenje sa drugim antenama često korišćenim u literaturi za datu svrhu. Izrađen je prototip komore sa predloženim antenama. Izvršena su merenja i poređenja sa predloženim modelom, kako bi se potvrdila verodostojsnost modela.Microwave tomography is method of object imaging by means of microwaves. After object measurement by system of antennas in chamber inverse problem is solved by numeric simulation and optimization. This thesis focuses on problem of trueness in modeling antenna system in simulation. Avoding approximations while modeling antenna system yield better trueness of software model. To achieve this target wire square spiral antenna is utilized in imaging chamber. Usage of proposed antenna in microwave tomography is novelty. Software simulation model of chamber with proposed antenna is designed and evaluated. Comparison with other antennas often used in literature for this purpose is done in simulation. Chamber with antennas is realized at the prototype level. Measurement and comparison with proposed model are done in order to verify its trueness

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process