Digital LDO modelling techniques for performance estimation at early design stage

This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated

Hierarchical Agent-based Adaptation for Self-Aware Embedded Computing Systems

Siirretty Doriast

Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

Active timing margin management to improve microprocessor power efficiency

Improving power/performance efficiency is critical for today’s micro- processors. From edge devices to datacenters, lower power or higher performance always produces better systems, measured by lower cost of ownership or longer battery time. This thesis studies improving microprocessor power/performance efficiency by optimizing the pipeline timing margin. In particular, this thesis focuses on improving the efficacy of Active Timing Margin, a young technology that dynamically adjusts the margin. Active timing margin trims down the pipeline timing margin with a control loop that adjusts voltage and frequency based on real-time chip environment monitoring. The key insight of this thesis is that in order to maximize active timing margin’s efficiency enhancement benefits, synergistic management from processor architecture design and system software scheduling are needed. To that end, this thesis covers the major consumers of pipeline timing margin, including temperature, voltage, and process variation. For temperature variation, the thesis proposes a table-lookup based active timing margin mechanism, and an associated temperature management scheme to minimize power consumption. For voltage variation, the thesis characterizes the limiting factors of adaptive clocking’s power saving and proposes application scheduling to maximize total system power reduction. For process variation, the thesis proposes core-level adaptive clocking reconfiguration to automatically expose inter-core variation and discusses workload scheduling and throttling management to control critical application performance. The author believes the optimization presented in this thesis can potentially benefit a variety of processor architectures as the conclusions are based on the solid measurement on state-of-the-art processors, and the research objective, active timing margin, already has wide applicability in the latest microprocessors by the time this thesis is written.Electrical and Computer Engineerin

On-chip adaptive power management for WPT-Enabled IoT

Internet of Things (IoT), as broadband network connecting every physical objects, is becoming more widely available in various industrial, medical, home and automotive applications. In such network, the physical devices, vehicles, medical assistance, and home appliances among others are supposed to be embedded by sensors, actuators, radio frequency (RF) antennas, memory, and microprocessors, such that these devices are able to exchange data and connect with other devices in the network. Among other IoT’s pillars, wireless sensor network (WSN) is one of the main parts comprising massive clusters of spatially distributed sensor nodes dedicated for sensing and monitoring environmental conditions. The lifetime of a WSN is greatly dependent on the lifetime of the small sensor nodes, which, in turn, is primarily dependent on energy availability within every sensor node. Predominantly, the main energy source for a sensor node is supplied by a small battery attached to it. In a large WSN with massive number of deployed sensor nodes, it becomes a challenge to replace the batteries of every single sensor node especially for sensor nodes deployed in harsh environments. Consequently, powering the sensor nodes becomes a key limiting issue, which poses important challenges for their practicality and cost. Therefore, in this thesis we propose enabling WSN, as the main pillar of IoT, by means of resonant inductive coupling (RIC) wireless power transfer (WPT). In order to enable efficient energy delivery at higher range, high quality factor RIC-WPT system is required in order to boost the magnetic flux generated at the transmitting coil. However, an adaptive front-end is essential for self-tuning the resonant tank against any mismatch in the components values, distance variation, and interference from close metallic objects. Consequently, the purpose of the thesis is to develop and design an adaptive efficient switch-mode front-end for self-tuning in WPT receivers in multiple receiver system. The thesis start by giving background about the IoT system and the technical bottleneck followed by the problem statement and thesis scope. Then, Chapter 2 provides detailed backgrounds about the RIC-WPT system. Specifically, Chapter 2 analyzes the characteristics of different compensation topologies in RIC-WPT followed by the implications of mistuning on efficiency and power transfer capability. Chapter 3 discusses the concept of switch-mode gyrators as a potential candidate for generic variable reactive element synthesis while different potential applications and design cases are provided. Chapter 4 proposes two different self-tuning control for WPT receivers that utilize switch-mode gyrators as variable reactive element synthesis. The performance aspects of control approaches are discussed and evaluated as well in Chapter 4. The development and exploration of more compact front-end for self-tuned WPT receiver is investigated in Chapter 5 by proposing a phase-controlled switched inductor converter. The operation and design details of different switch-mode phase-controlled topologies are given and evaluated in the same chapter. Finally, Chapter 6 provides the conclusions and highlight the contribution of the thesis, in addition to suggesting the related future research topics.Internet de las cosas (IoT), como red de banda ancha que interconecta cualquier cosa, se está estableciendo como una tecnología valiosa en varias aplicaciones industriales, médicas, domóticas y en el sector del automóvil. En dicha red, los dispositivos físicos, los vehículos, los sistemas de asistencia médica y los electrodomésticos, entre otros, incluyen sensores, actuadores, subsistemas de comunicación, memoria y microprocesadores, de modo que son capaces de intercambiar datos e interconectarse con otros elementos de la red. Entre otros pilares que posibilitan IoT, la red de sensores inalámbricos (WSN), que es una de las partes cruciales del sistema, está formada por un conjunto masivo de nodos de sensado distribuidos espacialmente, y dedicados a sensar y monitorizar las condiciones del contexto de las cosas interconectadas. El tiempo de vida útil de una red WSN depende estrechamente del tiempo de vida de los pequeños nodos sensores, los cuales, a su vez, dependen primordialmente de la disponibilidad de energía en cada nodo sensor. La fuente principal de energía para un nodo sensor suele ser una pequeña batería integrada en él. En una red WSN con muchos nodos y con una alta densidad, es un desafío el reemplazar las baterías de cada nodo sensor, especialmente en entornos hostiles, como puedan ser en escenarios de Industria 4.0. En consecuencia, la alimentación de los nodos sensores constituye uno de los cuellos de botella que limitan un despliegue masivo práctico y de bajo coste. A tenor de estas circunstancias, en esta tesis doctoral se propone habilitar las redes WSN, como pilar principal de sistemas IoT, mediante sistemas de transferencia inalámbrica de energía (WPT) basados en acoplamiento inductivo resonante (RIC). Con objeto de posibilitar el suministro eficiente de energía a mayores distancias, deben aumentarse los factores de calidad de los elementos inductivos resonantes del sistema RIC-WPT, especialmente con el propósito de aumentar el flujo magnético generado por el inductor transmisor de energía y su acoplamiento resonante en recepción. Sin embargo, dotar al cabezal electrónico que gestiona y condicionada el flujo de energía de capacidad adaptativa es esencial para conseguir la autosintonía automática del sistema acoplado y resonante RIC-WPT, que es muy propenso a la desintonía ante desajustes en los parámetros nominales de los componentes, variaciones de distancia entre transmisor y receptores, así como debido a la interferencia de objetos metálicos. Es por tanto el objetivo central de esta tesis doctoral el concebir, proponer, diseñar y validar un sistema de WPT para múltiples receptores que incluya funciones adaptativas de autosintonía mediante circuitos conmutados de alto rendimiento energético, y susceptible de ser integrado en un chip para el condicionamiento de energía en cada receptor de forma miniaturizada y desplegable de forma masiva. La tesis empieza proporcionando una revisión del estado del arte en sistemas de IoT destacando el reto tecnológico de la alimentación energética de los nodos sensores distribuidos y planteando así el foco de la tesis doctoral. El capítulo 2 sigue con una revisión crítica del statu quo de los sistemas de transferencia inalámbrica de energía RIC-WPT. Específicamente, el capítulo 2 analiza las características de diferentes estructuras circuitales de compensación en RIC-WPT seguido de una descripción crítica de las implicaciones de la desintonía en la eficiencia y la capacidad de transferencia energética del sistema. El capítulo 3 propone y explora el concepto de utilizar circuitos conmutados con función de girador como potenciales candidatos para la síntesis de propósito general de elementos reactivos variables sintonizables electrónicamente, incluyendo varias aplicaciones y casos de uso. El capítulo 4 propone dos alternativas para métodos y circuitos de control para la autosintonía de receptores de energíaPostprint (published version

Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip

In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core. For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed. The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed. The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications. Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können. Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren. Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien

Navigation/traffic control satellite mission study. Volume 3 - Selected navigation/ traffic control satellite system analysis and equipment definition Final report

L band and VHF voice communication in satellite navigation and traffic control networ

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Space Programs Summary No. 37-50, Volume 1 for the Period January 1 to February 29, 1968. Flight Projects

Systems analysis and engineering data on Mariner Venus 67, Mariner 4, Mariner Mars 69, and Surveyor projects, and advanced planetary missions technolog