Integrated Circuits and Systems for Millimeter-Wave Frequencies

In the first section of this thesis, mm-wave circuit- and system-level solutions for addition of multi-user service to conventional multi-antenna phased array architectures will be introduced. The proposed architecture will enhance the link capacity, co-channel user service and hardware cost compared to conventional solutions. Theory and design of the circuits and system are detailed and comprehensive measurement results are presented verifying the system-level functionality. First section is named A Millimeter-Wave Partially-Overlapped Beamforming-MIMO Receiver: Theory, Design, and Implementation. More specifically, this section presents an analysis and design of a partially-overlapped beamforming-MIMO architecture capable of achieving higher beamforming and spatial multiplexing gains with lower number of elements compared to conventional architectures. As a proof of concept, a 4-element beamforming-MIMO receiver (RX) covering 64-67 GHz frequency band enabling 2-stream concurrent reception is designed and measured. By partitioning the RX elements into two clusters and partially overlapping these clusters to create two 3-element beamformers, both phased-array (coherent beamforming) as well as MIMO (spatial multiplexing) features are simultaneously acquired. 6-bit phase shifters with 360° phase control and 5-bit VGAs with 11 dB range are designed to enable steering of the two RX clusters toward two arbitrary angular locations corresponding to two users. Fabricated in a 130-nm SiGe BiCMOS process, the RX achieves a 30.15 dB maximum direct conversion gain and a 9.8 dB minimum noise figure (NF) across 548 MHz IF bandwidth. S-parameter-based array factor measurements verify spatial filtering of the interference and spatial multiplexing in this RX chip.In the second section of this thesis, energy-efficient ultra-high speed transceiver architectures will be presented. Current high-speed transceivers rely on high-sampling-rate high-resolution power-hungry analog-to-digital converters or digital-to-analog converters at the interface of analog and digital circuitries. However, design of these backend data-converters are extremely power-hungry at very high speeds in a fully-integrated end-to-end scenario (i.e. RF-to-Bits, Bits-to-RF). Novel system-level architectures will be presented that obviate the need for such costly data converters and will significantly relax the complexity of digital signal-processing. The proposed architecture will result in orders of magnitude energy saving at ultra-high speeds. Theory, design, and measurement results of the highest-speed, highly energy-efficient fully-integrated end-to-end transceiver will be discussed in this section. Second section is named A Millimeter-Wave Energy-Efficient Direct-Demodulation Receiver: Theory, Design, and Implementation. More precisely, this section presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115-135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB was measured. A data-rate of 36 Gbps was wirelessly measured at 30 cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error-rate (BER) of 1e-6. The measured receiver sensitivity at this BER is -41.28 dBm. The prototype occupies 2.5 by 3.5 mm squared of die area including PADs and test circuits (2.5 mm squared active area) and consumes a total DC power of 200.25 mW

Modelling and performances assessment of OFDM and fast-OFDM wireless communication systems.

This thesis is mainly concerned with the design, modelling and performance assessment of modulation techniques for use in wireless communication systems. The work is divided, broadly in three areas; a multimode system proposal, an assessment of a new modulation scheme and a system optimisation technique. A multimode system architecture employing GSM and EDGE systems and an Orthogonal Frequency Division Multiplexing (OFDM) system is proposed. The OFDM system is designed to have similar frame structure, channel allocation and spectrum shape to those of the GSM and EDGE systems. The multimode system is evaluated under typical multipath fading environments specified for GSM/EDGE and adjacent-channel and co-channel interference. The results indicated that the proposed OFDM system can be perfectly integrated within the GSM/EDGE network core. Furthermore, a novel modulation technique is investigated. Fast-OFDM (FOFDM) is a variation of OFDM, which offers twice the bandwidth efficiency when compared to OFDM. However, the bandwidth efficiency only applies to one dimensional modulation schemes (BPSK or M-ASK). The suitability of FOFDM for wireless communications is assessed by studying its performance under receiver front-end distortions and multipath fading environments. The performance of the FOFDM system is compared with the performance of a similar OFDM system. The results indicated that under small distortion conditions, the performance of FOFDM and OFDM is comparable. Finally, the effect of interpolation filtering on OFDM systems in noise limited and interference limited environments is investigated. The aim of this study is to highlight that interference should be taken into consideration when designing systems for wireless communications. In addition, this study can be utilised in software defined radio schemes, offering optimised performance. Overall, this thesis presents work over a range of research areas, providing system proposals, modulation comparisons and system optimisation techniques that can be used by developers of future mobile systems

Low Power Analog Processing for Ultra-High-Speed Receivers with RF Correlation

Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the power-hungry ADCs, leading to low-power integrated design solutions

A Fully integrated D-band Direct-Conversion I/Q Transmitter and Receiver Chipset in SiGe BiCMOS Technology

This paper presents design and characterization of single-chip 110-170 GHz (D-band) direct conversion in-phase/quadrature-phase (I/Q) transmitter and receiver monolithic microwave integrated circuits (MMICs), realized in a 130 nm SiGe BiCMOS process with ft/fmax of 250 GHz/370 GHz. The chipset is suitable for low power wideband communication and can be used in both homodyne and heterodyne architectures. The Transmitter chip consists of a six-stage power amplifier, an I/Q modulator, and a LO multiplier chain. The LO multiplier chain consists of frequency sixtupler followed by a two-stage amplifier. It exhibits a single sideband conversion gain of 23 dB and saturated output power of 0 dBm. The 3 dB RF bandwidth is 31 GHz from 114 to 145 GHz. The receiver includes a low noise amplifier, I/Q demodulator and x6 multiplier chain at the LO port. The receiver provides a conversion gain of 27 dB and has a noise figure of 10 dB. It has 3 dB RF bandwidth of 28 GHz from 112-140 GHz. The transmitter and receiver have dc power consumption of 240 mW and 280 mW, respectively. The chip area of each transmitter and receiver circuit is 1.4 mm x 1.1 mm

Advanced Modulation and Coding Technology Conference

The objectives, approach, and status of all current LeRC-sponsored industry contracts and university grants are presented. The following topics are covered: (1) the LeRC Space Communications Program, and Advanced Modulation and Coding Projects; (2) the status of four contracts for development of proof-of-concept modems; (3) modulation and coding work done under three university grants, two small business innovation research contracts, and two demonstration model hardware development contracts; and (4) technology needs and opportunities for future missions

Recent Trends in Communication Networks

In recent years there has been many developments in communication technology. This has greatly enhanced the computing power of small handheld resource-constrained mobile devices. Different generations of communication technology have evolved. This had led to new research for communication of large volumes of data in different transmission media and the design of different communication protocols. Another direction of research concerns the secure and error-free communication between the sender and receiver despite the risk of the presence of an eavesdropper. For the communication requirement of a huge amount of multimedia streaming data, a lot of research has been carried out in the design of proper overlay networks. The book addresses new research techniques that have evolved to handle these challenges

Direct Antenna Modulation using Frequency Selective Surfaces

In the coming years, the number of connected wireless devices will increase dramatically, expanding the Internet of Things (IoT). It is likely that much of this capacity will come from network densification. However, base stations are inefficient and expensive, particularly the downlink transmitters. The main cause of this is the power amplifier (PA), which must amplify complex signals, so are expensive and often only 30% efficient. As such, the cost of densifying cellular networks is high. This thesis aims to overcome this problem through codesign of a low complexity, energy efficient transmitter through electromagnetic design; and a waveform which leverages the advantages and mitigates the disadvantages of the new technology, while being suitable for supporting IoT devices. Direct Antenna Modulation (DAM) is a low complexity transmitter architecture, where modulation occurs at the antenna at transmit power. This means a non-linear PA can efficiently amplify the carrier wave without added distortion. Frequency Selective Surfaces (FSS) are presented here as potential phase modulators for DAM transmitters. The theory of operation is discussed, and a prototype DAM for QPSK modulation is simulated, designed and tested. Next, the design process for a continuous phase modulating antenna is explored. Simulations and measurement are used to fully characterise a prototype, and it is implemented in a line-of-sight end-to-end communications system, demonstrating BPSK, QPSK and 8-PSK. Due to the favourable effects of spread spectrum signalling on FSS DAM performance, Cyclic Prefix Direct Sequence Spread Spectrum (CPDSSS) is developed. Conventional spreading techniques are extended using a cyclic prefix, making multipath interference entirely defined by the periodic autocorrelation of the sequence used. This is demonstrated analytically, through simulation and with experiments. Finally, CPDSSS is implemented using FSS DAM, demonstrating the potential of this new low cost, low complexity transmitter with CPDSSS as a scalable solution to IoT connectivity

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Adaptive equalizers for multipath compensation in digital microwave communications

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