Ultra high data rate CMOS FEs

The availability of numerous mm-wave frequency bands for wireless communication has motived the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performaning measurements using on-wafer probing at 60GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitiv to the effective length and bending of the interfaces. This paper presents different 60GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, A Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60GHZ integrated components and systems in the main stream CMOS technology

Ultra high data rate CMOS front ends

The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology

Voltage controlled oscillator for mm-wave radio systems

Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

TOWARDS LOW NOISE, HIGH POWER AND EFFICIENCY MM-WAVE AND TERAHERTZ CIRCUIT DESIGN

Mm-wave and terahertz frequency range is gaining vast attention in recent years due to attractive applications in various areas including spectroscopy, imaging, security and high data-rare communication. All these systems require high performance circuits for power generation and amplification. In recent years, many amplifiers and oscillators have been fabricated in SiGe and CMOS processes to show the feasibility of implementing these systems in this frequency range. Despite all the efforts and ideas employed to enhance the performance of these blocks, there is still a long way to go to achieve reasonably high performance amplifiers and signal sources at mm-wave and terahertz frequencies. The main challenge comes from the activity degradation of the transistors, high loss in the passives and high noise in the active and passive devices at this frequency range. In this work, new systematic design methods for low noise and highgain amplifiers and high power and efficiency oscillators at mm-wave and terahertz frequencies are presented. Chapter 1 reviews the basic concepts of the two-port networks such as stability, activity, power gains and noise parameters. These subjects are vastly used in the next chapters of this work when presenting the new methods for high frequency circuit design. In chapter 2, a new convex stability region is presented based on which, a systemic amplifier design method beyond fmax/2 is proposed which moves the network toward the high gain region using optimum passive embeddings. This method is capable of considering modeling errors of the components during the design process which results in a robust, stable and high gain amplifier. Employing this method, a three stage amplifier working at 173 GHz is designed and implemented in a 130 nm SiGe process which shows 18.5 dB gain, 8.2 GHz 3-dB bandwidth and 0.9 dBm saturated output power in the measurement. A new FoM is defined to fairly compare different amplifiers fabricatedindifferentprocesseswhichtargetsthecapabilityofthedesignmethodinextracting the power amplification potential of the active device. This amplifier achieves the highest FoM among all reported state of the arts works above fmax/2 in SiGe/CMOS processeswhichshowstheefficacyoftheproposedmethodinfullyutilizingtheprocess capabilities in amplifier design. In chapter 3, high frequency LNA is targeted and a systematic method to design low noise and high gain amplifier beyond fT/2 is presented. To achieve this goal, noise measure of the proposed structure becomes minimum employing optimum passive embeddings while the stability of the circuit is assured using the convex stability region derived in chapter 2. The guidelines and required noise and power equations to complete the systematic LNA design are derived and presented in this chapter. Employing this method,a 91 GHz LNA with 5.6dB noise figure,9.7 dB gain and 6.3 mW dc power consumption is implemented in a 130nm SiGe process. Comparing these results with the state of the arts using the proposed FoM that takes the process and power consumption into account justifies the effectiveness of this design method in fully utilizing low noise and high power generation capability of the process. A design methodology for high power mm-wave VCO design is presented in chapter 4. Using the complete passive embeddings including the load, the power gain from the input of the active device to the load is maximized which results in an oscillator with high power at the output and significantly improved DC-to-RF efficiency. In addition, the proposed structure is capable of providing sufficient tuning range which is an important factor in mm-wave source design and applications. A VCO working at 110 GHz is designed and implemented in a 55 nm SiGe process employing this method which shows 6.3 dBm peak output power, 20.9% DC-to-RF efficiency and 5.2% tuning range. This VCO achieves highest peak output power in F and D band (90 GHz to 170 GHz) and highest DC-to-RF efficiency in frequencies below fmax/2 among all reported mm-wave oscillators in SiGe/CMOS processes. Chapter 5 represents a new design method for high power and efficiency harmonic oscillator. This method exploits different mechanism to enhance the fundamental oscillator performance, increasing the harmonic power generation in the active device and effectively delivering the generated harmonic power to the load using various passive embeddings in a cross-coupled structure. Capacitive degeneration is employed to shape Gm of the structure. Inductive embeddings at the base of the transistors are utilized to provide sufficient voltage gain and increase harmonic current generation in the active device. The embeddings at the collector are used to maximize the output resistance of the structure which results in delivering majority of the generated current to the load. Employing this method, a 300 GHz harmonic oscillator is designed and implemented in a 130 nm SiGe process which shows 2.8 dBm peak output power and 4.5% DC-to-RF efficiency with 86.6 mW/mm2 power-area efficiency. Also, a harmonic VCO is implemented with 2.3 dBm peak output power, 3.5% DC-to-RF efficiency and 1.5% tuning range and 77.2 mW/mm2 power-area efficiency in the same process. This harmonic oscillator method significantly improves the power-area efficiency of high frequency signal sources and the designed oscillator achieves the highest power-area efficiency among all reported SiGe/CMOS oscillators working above 0.75 fmax

Novel RF CMOS Integrated Circuits and Systems for Broadband Dielectric Spectroscopy

Broadband dielectric spectroscopy has proven to be a valuable technique for characterization of chemicals and biomaterials. It has the great potential to become an indispensable and cost-effective tool in point-of-care medical applications due to its label-free and non-invasive operation. However, most of the existing dielectric spectroscopy instruments require bulky, heavy and expensive measurement set-up, restricting their use to only special applications in industry and laboratories. Therefore, integrated dielectric spectroscopy on silicon capable of direct detection of chemicals/biomaterials' complex permittivity can yield significant cost and size reduction, system integration, portability, enormous processing, and high throughput. A CMOS wideband dielectric spectroscopy system is proposed for chemical and biological material characterization. The complex permittivity detection is performed using a configurable harmonic-rejecting receiver capable of indirectly measuring the complex admittance of sensing capacitor exposed to the material-under-test (MUT) and subject to RF signal excitation with a frequency range of 0.62-10 GHz. The sensing capacitor is embedded in a voltage divider topology with a fixed capacitor and the relative variations in the magnitude and phase of the voltages across the capacitors are used to find the real and imaginary parts of the permittivity. The sensor achieves an rms permittivity error of less than 1% over the entire operation bandwidth. Using a sub-harmonic mixing scheme, the system can perform complex permittivity measurements from 0.62 to 10 GHz while requiring an input signal source with frequency range of only from 5 to 10 GHz. Thereby, the permittivity measurement system can be easily made self-sustained by implementing a 5-10 GHz frequency synthesizer on the same chip. One of the key building blocks in such a frequency synthesizer is the voltage-controlled oscillator (VCO) which has to cover an octave of frequency range. A novel low-phase-noise wide-tuning range VCO is presented using a triple-band LC resonator. The implemented VCO in 0.18μm CMOS technology achieves a continuous tuning range of 86.7% from 5.12 GHz to 12.95 GHz while drawing 5 to 10 mA current from 1-V supply. The measured phase noise at 1 MHz offset from carrier frequencies of 5.9, 9.12 and 12.25 GHz is -122.9, -117.1 and -110.5 dBc/Hz, respectively. Also, a dual-band quadrature voltage-controlled oscillator (QVCO) is presented using a transformer-based high-order LC-ring resonator which inherently provides quadrature signals without requiring noisy coupling transistors as in traditional approaches. The proposed resonator shows two possible oscillation frequencies which are exploited to realize a wide-tuning range QVCO employing a mode-switching transistor network. Due to the use of transformers, the oscillator has minimal area penalty compared to the conventional designs. The implemented prototype in a 65-nm CMOS process achieves a continuous tuning range of 77.8% from 2.75 GHz to 6.25 GHz while consuming 9.7 to 15.6 mA current from 0.6-V supply. The measured phase noise figure-of-merit (FoM) at 1 MHz offset ranges from 184 dB to 188.2 dB throughout the entire tuning range. The QVCO also exhibits good quadrature accuracy with 1.5º maximum phase error and occupies a relatively small silicon area of 0.35 mm^2

Scalable Array Transceivers with Wide Frequency Tuning Range for Next Generation Radios

Scalable array transceivers with wide frequency tuning range are attractive for next-generationradios. Key challenges for such radios include generation of LO signals with widefrequency tuning range, scalable synchronization between multiple array unit cells andtolerance to in-band and out-of-band interferers. This thesis presents approaches toaddress these challenges in commercial CMOS technologies.The first part focuses on a series resonant mode-switching VCO architecture thatachieves both state-of-art area and power efficiency with an octave frequency tuningrange from 6.4-14 GHz achieved 186-dB-188-dB Figure-of-Merit (FoM) in 65 nm CMOStechnology. The scalability of this approach towards achieving even larger FTR is alsodemonstrated by a triple-mode 2.2 GHz to 8.7 GHz (119% FTR) CMOS VCO.In the second part a scalable, single-wire coupled-PLL architecture for RF mm-wavearrays is presented. The proposed architecture preserves the simplicity of a daisy-chained LO distribution, compensates for phase offset due to interconnect, and provides phasenoise improvement commensurate to the number of coupled PLLs. Measurements on a28 GHz CMOS prototype demonstrate the feasibility of this scheme.The third part of this thesis presents filtering techniques for in-band blocker suppression.A spatial spectral notch filter design for MIMO digital beam forming arrays is proposedto relax the ADC dynamic range requirement. Orthogonal properties of Walsh functionsincorporated into passive N-path approach enables reconfigurable notches at multiplefrequencies and angles-of-incidence. A 0.3 GHz-1.4 GHz four-element array prototypeimplemented in 65 nm CMOS achieves > 15-dB notch filtering at RF input for twoblockers while causing < 3-dB NF degradation.Finally, a code-domain N-path receiver (RX) is proposed based on pseudo-random(PN) code-modulated LO pulses for simultaneous transmission and reception (STAR)applications. A combination of Walsh-Function and PN sequence is proposed to createcode-domain matched filter at the RF frontend which reflects unknown in-band blockersand rejects known in-band TX self-interference (SI) by using orthogonal codes at RXinput thereby maximizing the SNR of the received signals. The resulting prototype in65 nm is functional from 0.3 GHz-1.4 GHz with 35 dB gain and concurrently receivestwo code-modulated signals. Proposed transmitter (TX) SI mitigation approach resultsin 38.5 dB rejection for -11.8 dBm 1.46 Mb s QPSK modulated SI at RX input. TheRX achieves 23.7 dBm OP1dB for in-band SI, while consuming ∼35 mW and occupies0.31 mm2Keywords: Passive Mixers, dual band, TX self-Interferer, synchronisation, STAR, Code domain N-path receiver, mode switching, notch filter, Phase locked loops, Octave tuning range, CMOS, phase noise, VCO, large-scale 5G mm-wave arrays, resonator, Simultaneous transmit and receive, resonator band-switching, LO distribution, scalable coupled-PLL, N-path passive mixers, MIMO arrays, digital beamforming, CDMA, phased arrays, wide tuning range, Walsh Functio

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Integrated Circuit and Antenna Technology for Millimeter-wave Phased Array Radio Front-end

Ever growing demands for higher data rate and bandwidth are pushing extremely high data rate wireless applications to millimeter-wave band (30-300GHz), where sufficient bandwidth is available and high data rate wireless can be achieved without using complex modulation schemes. In addition to the communication applications, millimeter-wave band has enabled novel short range and long range radar sensors for automotive as well as high resolution imaging systems for medical and security. Small size, high gain antennas, unlicensed and worldwide availability of released bands for communication and a number of other applications are other advantages of the millimeter-wave band. The major obstacle for the wide deployment of commercial wireless and radar systems in this frequency range is the high cost and bulky nature of existing GaAs- and InP-based solutions. In recent years, with the rapid scaling and development of the silicon-based integrated circuit technologies such as CMOS and SiGe, low cost technologies have shown acceptable millimeter-wave performance, which can enable highly integrated millimeter-wave radio devices and reduce the cost significantly. Furthermore, at this range of frequencies, on-chip antenna becomes feasible and can be considered as an attractive solution that can further reduce the cost and complexity of the radio package. The propagation channel challenges for the realization of low cost and reliable silicon-based communication devices at millimeter-wave band are severe path loss as well as shadowing loss of human body. Silicon technology challenges are low-Q passive components, low breakdown voltage of active devices, and low efficiency of on-chip antennas. The main objective of this thesis is to investigate and to develop antenna and front-end for cost-effective silicon based millimeter-wave phased array radio architectures that can address above challenges for short range, high data rate wireless communication as well as radar applications. Although the proposed concepts and the results obtained in this research are general, as an important example, the application focus in this research is placed on the radio aspects of emerging 60 GHz communication system. For this particular but extremely important case, various aspects of the technology including standard, architecture, antenna options and indoor propagation channel at presence of a human body are studied. On-chip dielectric resonator antenna as a radiation efficiency improvement technique for an on-chip antenna on low resistivity silicon is presented, developed and proved by measurement. Radiation efficiency of about 50% was measured which is a significant improvement in the radiation efficiency of on-chip antennas. Also as a further step, integration of the proposed high efficiency antenna with an amplifier in transmit and receive configurations at 30 GHz is successfully demonstrated. For the implementation of a low cost millimeter-wave array antenna, miniaturized, and efficient antenna structures in a new integrated passive device technology using high resistivity silicon are designed and developed. Front-end circuit blocks such as variable gain LNA, continuous passive and active phase shifters are investigated, designed and developed for a 60GHz phased array radio in CMOS technology. Finally, two-element CMOS phased array front-ends based on passive and active phase shifting architectures are proposed, developed and compared

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2