High-speed high-resolution low-power self-calibrated digital-to-analog converters

High-speed and high-resolution low-power digital-to-analog converters (DACs) are basic design blocks in many applications. Several obvious conflicting requirements such as high-speed, high-resolution, low-power, and small-area have to be satisfied. In this dissertation, a modular architecture for continuous self-calibrating DACs is proposed to satisfy the above requirements. This includes a redundant-cell-relay continuous self-calibration scheme. Several prototype DACs were implemented with self-calibration schemes. Also a DAC synthesis algorithm using a direct-mapping method and the modular structure was developed and implemented in the Cadence SKILL programming language.;One of the prototypes is a 250MS/s 8-bit continuous self-calibrated DAC that has been implemented in TSMC\u27s 0.25mu single poly five metal logic CMOS process. The structure of the self-calibrated current cell has high impedance and low sensitivity to output node voltage fluctuations. The chip has achieved +0.15/-0.1 LSB DNL, -0.6/+0.4 LSB INL, and 55dB SFDR with a lower input frequency at a conversion rate of 250MS/s. It consumes 8 mW of power in a 0.13 mm2 die area.;Glitches caused by switching of the calibration clock degrade the SFDR especially in high-speed applications. A new redundant-cell-relay continuous self-calibration scheme was proposed to reduce the glitches. Simulation results showed that the glitch energy is reduced 10 fold over existing schemes. A 10-bit DAC was implemented in the 0.25mu CMOS process mentioned above. +/-0.5 LSB INL and -0.45/+0.2 LSB DNL were measured and 70dB SFDR was achieved with a lower input frequency at a 250MS/s conversion rate. Up to the Nyquist rate, the SFDR is above 53dB at a conversion rate of 200MS/s. The DAC dissipates 8mW in a 0.3mm2 die area. The testing results verified the redundant-cell-relay continuous self-calibration for high-speed high-resolution low-power and low-cost DACs.;Additionally, a DAC synthesis algorithm was developed based on a direct mapping method. Given the specifications such as the DAC\u27s resolution, full range scale and technology, the synthesizer will map them directly into pre-existing functional blocks implemented in the DAC synthesis libraries. The program will then synthesize the schematic and layout that closely meet the given specifications

Design and implementation of 4 bit binary weighted current steering DAC

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation

High-speed Design Of High-resolution Dacs

Tez (Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2009Thesis (PhD) -- İstanbul Technical University, Institute of Science and Technology, 2009Bu çalışmada, yüksek çözünürlüklü akım yönlendirmeli sayısal-analog dönüştürücülerin (SAD) hızlı tasarımını sağlayan yöntemler incelenmekte ve yeni yaklaşımlar önerilmektedir. Veri dönüştürücüler analog ve sayısal dünyalar arasında bir köprü oluşturdukları için hızlı ve verimli bir şekilde gerçekleştirilmeleri yüksek derecede arzu edilmektedir. Yüksek hızlı (birkaç 100MHz) ve yüksek çözünürlüklü (10 bitten fazla) SAD için artan rağbet, akım yönlendirmeli SADların kullanımını zorunlu kılmaktadır. Yüksek performanslı akım yönlendirmeli SADların tasarımında ve gerçekleştirmesinde kesimleme (segmentation) yöntemi kullanılmaktadır. Bu yöntem, yüksek hız ve yüksek çözünürlük gerektiren uygulamaların çoğunda avantajlı olmasına rağmen uzun süreli tasarım zamanı, karmaşıklık ve yüksek maliyet yüzünden değer kaybetmektedir. Böylece, bazı uygulamalar için zaman ve maliyet açısından bu yöntemin kullanılması hızlı ve verimli olmayabilir. Bu problemlerin üstesinden gelmek için yüksek çözünürlüklü SADların yüksek hızlı tasarımını sağlayan hızlı ve verimli yöntemler dikkate alınmaktadır. Uygun bir tasarım yöntemi ve yeni bir yapı önerilmektedir. Akım yönlendirmeli SADlar gibi karmaşık karma yapılı sistemlerin tasarımı için davranışsal modelin oluşturulması zorunlu olmaktadır. Bu amaçla gerçekleştirilen modellerin çoğu sistemin davranışı hakkında istenilen eksiksiz manzarayı vermemektedir. Bu yüzden, transistor seviyesindeki tasarıma geçmeden önce, tasarımı hızlandırabilen ve sistemin davranışını doğru bir şekilde yansıtabilen modeller geliştirilmektedir. SIMULINK® kullanılarak bir davranışsal model kurulmakta ve modelin performansı benzetimlerle sınanmaktadır. Sonuç olarak, uygulanan yöntemin verimliliğini ve davranışsal modelin doğruluğunu sınamak için 0.35µm CMOS proses teknolojisi için tasarlanan bir 12 bitlik melez akım yönlendirmeli SAD kullanılmaktadır. Yapı bloklarında yapılan iyileştirmeler ve kullanılan farklı yöntemler, gerçekleştirilen SAD’ın serimindeki ilgili kısımlarda yer almaktadırlar. CADENCE Geleneksel Tümleşik Devre Tasarım Araçları kullanılarak serim sonrası benzetimleri yapılmakta ve SAD’ın performans karakteristikleri incelenmektedir.In this thesis, different problems related to the design speed-up of high-resolution current-steering digital-to-analog converters (DAC) are addressed and novel solutions are proposed. Since data converters form the bridge between the analog and digital world their efficient implementation is highly desirable. The increase in demand for high-speed (several 100MHz) and high-resolution (higher than 10-bit) DAC, forces the use of current-steering DACs. Segmentation method is used for the design and the implementation of high performance current-steering DACs. Although this methodology is advantageous in most of the applications requiring high-speed and high-resolution, it suffers from the prolonged design time, complexity and high cost. Thus, the use of this methodology for some applications is not efficient concerning the time and the cost. To overcome these problems efficient methodologies for the high-speed design of high-resolution DACs are considered. A proper design methodology and a novel architecture are introduced. Behavioral modeling is necessary for the design of complex mixed-mode systems like current-steering DACs. Most of the models constructed can not give a complete view of the system’s behavior. For this reason, models that speed up the design and reflect accurately the behavior of the system prior to transistor level implementation are developed. A SIMULINK® based behavioral model is developed and verified through simulations. To conclude, the efficiency of the applied methodology and the accuracy of the behavioral model are validated through the implementation of a 12-bit hybrid current-steering DAC in a 0.35µm CMOS process technology. The improvements in the building blocks and the different approaches used are reflected in the respective parts of the layout of the implemented DAC. Post-layout simulations are obtained using CADENCE Custom IC Design Tools and the performance metrics of the DAC are investigated.DoktoraPh

Smart and high-performance digital-to-analog converters with dynamic-mismatch mapping

The trends of advanced communication systems, such as the high data rate in multi-channel base-stations and digital IF conversion in software-defined radios, have caused a continuously increasing demand for high performance interface circuits between the analog and the digital domain. A Digital-to-Analog converter (DAC) is such an interface circuit in the transmitter path. High bandwidth, high linearity and low noise are the main design challenges in high performance DACs. Current-steering is the most suitable architecture to meet these performance requirements. The aim of this thesis is to develop design techniques for high-speed high-performance Nyquist current-steering DACs, especially for the design of DACs with high dynamic performance, e.g. high linearity and low noise. The thesis starts with an introduction to DACs in chapter 2. The function in time/frequency domain, performance specifications, architectures and physical implementations of DACs are brie y discussed. Benchmarks of state-of-the-art published Nyquist DACs are also given. Chapter 3 analyzes performance limitations by various error sources in Nyquist current-steering DACs. The outcome shows that in the frequency range of DC to hundreds of MHz, mismatch errors, i.e. amplitude and timing errors, dominate the DAC linearity. Moreover, as frequencies increase, the effect of timing errors becomes more and more dominant over that of amplitude errors. Two new parameters, i.e. dynamic-INL and dynamic-DNL, are proposed to evaluate the matching of current cells. Compared to the traditional static-INL/DNL, the dynamic-INL/DNL can describe the matching between current cells more accurately and completely. By reducing the dynamic-INL/DNL, the non-linearities caused by all mismatch errors can be reduced. Therefore, both the DAC static and dynamic performance can be improved. The dynamic-INL/DNL are frequency-dependent parameters based on the measurement modulation frequency fm. This fm determines the weight between amplitude and timing errors in the dynamic-INL/DNL. Actually, this gives a freedom to optimize the DAC performance for different applications, e.g. low fm for low frequency applications and high fm for high frequency applications. Chapter 4 summarizes the existing design techniques for intrinsic and smart DACs. Due to technology limitations, it is diffcult to reduce the mismatch errors just by intrinsic DAC design with reasonable chip area and power consumption. Therefore, calibration techniques are required. An intrinsic DAC with calibration is called a smart DAC. Existing analog calibration techniques mainly focus on current source calibration, so that the amplitude error can be reduced. Dynamic element matching is a kind of digital calibration technique. It can reduce the non-linearities caused by all mismatch errors, but at the cost of an increased noise oor. Mapping is another kind of digital calibration technique and will not increase the noise. Mapping, as a highly digitized calibration technique, has many advantages. Since it corrects the error effects in the digital domain, the DAC analog core can be made clean and compact, which reduces the parasitics and the interference generated in the analog part. Traditional mapping is static-mismatch mapping, i.e. mapping only for amplitude errors, which many publications have already addressed on. Several concepts have also been proposed on mapping for timing errors. However, just mapping for amplitude or timing error is not enough to guarantee a good performance. This work focuses on developing mapping techniques which can correct both amplitude and timing errors at the same time. Chapter 5 introduces a novel mapping technique, called dynamic-mismatch mapping (DMM). By modulating current cells as square-wave outputs and measuring the dynamic-mismatch errors as vectors, DMM optimizes the switching sequence of current cells based on dynamic-mismatch error cancelation such that the dynamic-INL can be reduced. After reducing the dynamic-INL, the non-linearities caused by both amplitude and timing errors can be significantly reduced in the whole Nyquist band, which is confirmed by Matlab behavioral-level Monte-Carlo simulations. Compared to traditional static-mismatch mapping (SMM), DMM can reduce the non-linearities caused by both amplitude and timing errors. Compared to dynamic element matching (DEM), DMM does not increase the noise floor. The dynamic-mismatch error has to be accurately measured in order to gain the maximal benefit from DMM. An on-chip dynamic-mismatch error sensor based on a zero-IF receiver is proposed in chapter 6. This sensor is especially designed for low 1/f noise since the signal is directly down-converted to DC. Its signal transfer function and noise analysis are also given and con??rmed by transistor-level simulations. Chapter 7 gives a design example of a 14-bit current-steering DAC in 0.14mum CMOS technology. The DAC can be configured in an intrinsic-DAC mode or a smart-DAC mode. In the intrinsic-DAC mode, the 14-bit 650MS/s intrinsic DAC core achieves a performance of SFDR>65dBc across the whole 325MHz Nyquist band. In the smart-DAC mode, compared to the intrinsic DAC performance, DMM improves the DAC performance in the whole Nyquist band, providing at least 5dB linearity improvement at 200MS/s and without increasing the noise oor. This 14-bit 200MS/s smart DAC with DMM achieves a performance of SFDR>78dBc, IM

Digital signal processing and digital-to-analog converters for wide-band transmitters

In this thesis, the implementation methods of digital signal processing and digital-to-analog converters for wide-band transmitters are researched. With digital signal processing, the problems of analog signal processing, such as sensitivity to interference and nonidealities of the semiconductor processes, can be avoided. Also, the programmability can be implemented digitally more easily than by means of analog signal processing. During the past few years, wireless communications has evolved from analog to digital, and signal bandwidths have increased, enabling faster and faster data transmission. The evolution of semiconductor processes, decreasing linewidth and supply voltages, has decreased the size of the electronics and power dissipation, enabling the integration of larger and larger systems on single silicon chips. There is little overall benefit in decreasing linewidths to meet the needs of analog design, since it makes the design process more difficult as the device sizes cannot be scaled according to minimum linewidth and because of the decreasing supply voltage. On the other hand, the challenges of digital signal processing are related to the efficient realization of signal processing algorithms in such a way that the required area and power dissipation does not increase extensively. In this book, the problems related to digital filters, upconversion algorithms and digital-to-analog converters used in digital transmitters are researched. Research results are applied to the implementation of a transmitter for a third-generation WCDMA base-station. In addition, the theory of factors affecting the linearity and performance of digital-to-analog converters is researched, and a digital calibration algorithm for enhancement of the static linearity has been presented. The algorithm has been implemented together with a 16-bit converter; its functionality has been demonstrated with measurements.Tässä väitöskirjassa on tutkittu digitaalisen signaalinkäsittelyn toteuttamista ja digitaalisesta analogiseksi -muuntimia laajakaistaisiin lähettimiin. Digitaalisella signaalinkäsittelyllä voidaan välttää monia analogiseen signaalinkäsittelyyn liittyviä ongelmia, kuten häiriöherkkyyttä ja puolijohdeprosessien epäideaalisuuksien vaikutuksia. Myös ohjelmoitavuus on helpommin toteutettavissa digitaalisesti kuin analogisen signaalinkäsittelyn keinoin. Viime vuosina on langattomien tietoliikennejärjestelmien kehitys kulkenut analogisesta digitaaliseen, ja käytettävät signaalikaistanleveydet ovat kasvaneet mahdollistaen yhä nopeamman tiedonsiirron. Puolijohdeprosessien kehitys, kapeneva minimiviivanleveys ja pienemmät käyttöjännitteet, on pienentänyt elektroniikan kokoa ja tehonkulutusta mahdollistaen yhä suurempien kokonaisuuksien integroimisen yhdelle piisirulle. Viivanleveyksien pieneneminen ei kuitenkaan suoraan hyödytä analogiasuunnittelua, jossa piirielementtien kokoa ei välttämättä voida pienentää viivanleveyden pienentyessä, ja jossa madaltuva käyttöjännite ennemminkin hankaloittaa kuin helpottaa suunnittelua. Siksi yhä suurempi osa signaalinkäsittelystä pyritään tekemään digitaalisesti. Digitaalisen signaalinkäsittelyn ongelmat puolestaan liittyvät algoritmien tehokkaaseen toteuttamiseen siten, että piirien pinta-ala ja tehonkulutus eivät kasva liian suuriksi. Tässä kirjassa on tutkittu digitaalisessa lähettimessä tarvittavien digitaalisten suodattimien, ylössekoitusalgoritmien ja digitaalisesta analogiseksi -muuntimien toteuttamiseen liittyviä ongelmia. Tutkimustuloksia on sovellettu kolmannen sukupolven WCDMA-tukiasemalähettimen toteutuksessa. Lisäksi on tutkittu digitaalisesta analogiseksi -muuntimien lineaarisuuteen ja suorituskykyyn vaikuttavien seikkojen teoriaa, ja esitetty digitaalinen kalibrointialgoritmi muuntimen staattisen suorituskyvyn parantamiseksi. Algoritmi on toteutettu 16-bittisen muuntimen yhteydessä ja se on osoitettu toimivaksi mittauksin.reviewe

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Power and spectrally efficient integrated high-speed LED drivers for visible light communication

Recent trends in mobile broadband indicates that the available radio frequency (RF) spectrum will not be enough to support the data requirements of the immediate future. Visible light communication, which uses visible spectrum to transmit wirelessly could be a potential solution to the RF ’Spectrum Crunch’. Thus there is growing interest all over the world in this domain with support from both academia and industry. Visible light communication( VLC) systems make use of light emitting diodes (LEDs), which are semiconductor light sources to transmit information. A number of demonstrators at different data capacity and link distances has been reported in this area. One of the key problems holding this technology from taking off is the unavailability of power efficient, miniature LED drive schemes. Reported demonstrators, mostly using either off the shelf components or arbitrary waveform generators (AWGs) to drive the LEDs have only started to address this problem by adopting integrated drivers designed for driving lighting installations for communications. The voltage regulator based drive schemes provide high power efficiency (> 90 %) but it is difficult to realise the fast switching required to achieve the Mbps or Gbps data rates needed for modern wireless communication devices. In this work, we are exploiting CMOS technology to realise an integrated LED driver for VLC. Instead of using conventional drive schemes (digital to analogue converter (DAC) + power amplifier or voltage regulators), we realised a current steering DAC based LED driver operating at high currents and sampling rates whilst maintaining power efficiency. Compared to a commercial AWG or discrete LED driver, circuit realised utilisng complementary metal oxide semiconductor (CMOS) technology has resulted in area reduction (29mm2). We realised for the first time a multi-channel CMOS LED driver capable of operating up to a 500 MHz sample rate at an output current of 255 mA per channel and >70% power efficiency. We were able to demonstrate the flexibility of the driver by employing it to realise VLC links using micro LEDs and commercial LEDs. Data rates up to 1 Gbps were achieved using this system employing a multiple input, multiple output (MIMO) scheme. We also demonstrated the wavelength division multiplexing ability of the driver using a red/green/blue commercial LED. The first integrated digital to light converter (DLC), where depending on the input code, a proportional number of LEDs are turned ON, realising a data converter in the optical domain, is also an output from this research. In addition, we propose a differential optical drive scheme where two output branches of a current DAC are used to drive two LEDs achieving higher link performance and power efficiency compared to single LED drive

Low-power ADC designs in scaled CMOS process

This thesis presents advanced design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs), continuous-time ∆Σ ADCs, and single-slope (SS) ADCs in nano-scale CMOS technologies. (1) In high-speed SAR ADCs, metastability of the comparator limits the performance, which even results in the sparkle code errors. Proposed background calibration utilizing the comparator decision time detector removes the metastability-induced sparkle code errors by controlling the metastability detection window. At the same time, 1-bit resolution increase is gained from the proposed technique, which results in the fewer comparison cycles. Along with the relaxed requirement on the comparator, this cycle reduction helps to achieve the good power efficiency in high-speed SAR design. A prototype ADC in 40nm CMOS achieves 35.3dB SNDR and consumes 0.81mW while sampling at 700MS/s. (2) In the proposed continuous-time ∆Σ ADCs, conventional power-hungry opamp is replaced by voltage controlled oscillators (VCOs) that perform the data conversion in the phase domain instead of the voltage domain. In contrary to the opamp which is difficult to achieve good performance in the advanced CMOS process, VCOs have many advantages in the phase domain. To solve the nonlinear gain of VCOs, dual VCO-based integrator is used to suppress the dominant second-order distortion. To address the distortion from the DAC, a novel DAC calibration technique that both digitally senses and removes DAC mismatch errors is proposed. It has low hardware complexity by taking advantage of the intrinsic clocked level averaging (CLA) capability of dual-VCO-based integrator. It ensures high linearity regardless of the VCO center frequency. By lowering the VCO center frequency, power consumption is reduced. A prototype ADC designed in 130nm occupies an area of only 0.04mm² . It achieves 71dB SNDR over 1.7MHz bandwidth (BW) while sampling at 250MS/s and consuming only 0.9mW from a 1.2V power supply. The corresponding figure-of-merit (FOM) is 98 fJ/conversion-step. (3) A SS ADC has advantages of high linearity and a simple architecture. Thus, it is well suited for the column-parallel architecture for the CMOS image sensors. However, conversion speed is severely limited in high-bit resolution since more than 2 [superscript N] cycles are required for a N-bit resolution. To tackle this limitation, a two-step approach becomes popular. In this thesis, a two-step SAR/SS architecture is presented. In addition to reducing the conversion time, analog correlated double sampling (CDS) can cancel kT/C noise, which enables capacitor area reduction. A prototype ADC in 180nm CMOS occupies only 9.3µm x 830µm. It achieves 60.5dB SNR after CDS while sampling at 256kHz and consuming 91µWElectrical and Computer Engineerin