Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Low-power ADC designs in scaled CMOS process

This thesis presents advanced design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs), continuous-time ∆Σ ADCs, and single-slope (SS) ADCs in nano-scale CMOS technologies. (1) In high-speed SAR ADCs, metastability of the comparator limits the performance, which even results in the sparkle code errors. Proposed background calibration utilizing the comparator decision time detector removes the metastability-induced sparkle code errors by controlling the metastability detection window. At the same time, 1-bit resolution increase is gained from the proposed technique, which results in the fewer comparison cycles. Along with the relaxed requirement on the comparator, this cycle reduction helps to achieve the good power efficiency in high-speed SAR design. A prototype ADC in 40nm CMOS achieves 35.3dB SNDR and consumes 0.81mW while sampling at 700MS/s. (2) In the proposed continuous-time ∆Σ ADCs, conventional power-hungry opamp is replaced by voltage controlled oscillators (VCOs) that perform the data conversion in the phase domain instead of the voltage domain. In contrary to the opamp which is difficult to achieve good performance in the advanced CMOS process, VCOs have many advantages in the phase domain. To solve the nonlinear gain of VCOs, dual VCO-based integrator is used to suppress the dominant second-order distortion. To address the distortion from the DAC, a novel DAC calibration technique that both digitally senses and removes DAC mismatch errors is proposed. It has low hardware complexity by taking advantage of the intrinsic clocked level averaging (CLA) capability of dual-VCO-based integrator. It ensures high linearity regardless of the VCO center frequency. By lowering the VCO center frequency, power consumption is reduced. A prototype ADC designed in 130nm occupies an area of only 0.04mm² . It achieves 71dB SNDR over 1.7MHz bandwidth (BW) while sampling at 250MS/s and consuming only 0.9mW from a 1.2V power supply. The corresponding figure-of-merit (FOM) is 98 fJ/conversion-step. (3) A SS ADC has advantages of high linearity and a simple architecture. Thus, it is well suited for the column-parallel architecture for the CMOS image sensors. However, conversion speed is severely limited in high-bit resolution since more than 2 [superscript N] cycles are required for a N-bit resolution. To tackle this limitation, a two-step approach becomes popular. In this thesis, a two-step SAR/SS architecture is presented. In addition to reducing the conversion time, analog correlated double sampling (CDS) can cancel kT/C noise, which enables capacitor area reduction. A prototype ADC in 180nm CMOS occupies only 9.3µm x 830µm. It achieves 60.5dB SNR after CDS while sampling at 256kHz and consuming 91µWElectrical and Computer Engineerin

A Column-parallel Single-Slope ADC with Signal-Dependent Multiple Sampling Technique for CMOS Image Sensor

Department of Electrical EngineeringBoth Charge-Coupled Device (CCD) and Complementary Metal-Oxide Semiconductor (CMOS) image sensor have same starting point ??? they convert light photons into electrons. Recently, CMOS image sensor (CIS) has been developed significantly. CIS is much less expensive to manufacture than CCD sensor. Also, CIS has advantages over high speed, low noise and low power consumption. Therefore, such features can be used for many applications. In general, CIS has the number of incoming photons dependent noise characteristics. In the bright condition, photon shot noise is dominant in CIS compared with other noise sources. Photon shot noise cannot be reduced by circuit technique in single frame. However, CIS has high SNR in bright condition because the slope of the increase in signal is faster than the slope of increase in noise. But, in the dark condition, photon shot noise is not dominant in CIS. Random noises have dominance In CIS in the dark condition. These effects of noises can be reduced by circuit techniques. In the same way, Indirect Time-of-Flight (I-TOF) sensor has similar characteristics. When it measures long distance, its depth accuracy is reduced because of lack of incoming photons same as CIS in the dark condition. Therefore, same circuit technique can be used for pursuing beneficial effects on CIS and I- TOF sensor. To increase SNR in CIS, imposing gain in correlated double sampling stage as pre-amplifier. Therefore, it can increase SNR and reducing effects of readout random noises. However, it cannot increase gain highly as we want because of saturation problem and large power consumption. Therefore, it is not an advantageous method of low power systems. Otherwise, the multiple sampling technique had been proposed. It averages out all of the readout random noises by sampling several times [7]. Therefore, noise power is reduced in the inverse of sampling number and in voltage domain, noise rms value is reduced in the inverse of square root of sampling number. However, sampling several times increases readout time which is proportional to sampling number significantly. Therefore, to alleviate trade-offs coming from multiple sampling, several approaches is developed in the past. Typical examples are signal-dependent multiple sampling technique, pseudo multiple sampling technique and conditional multiple sampling technique. First, the pseudo multiple sampling technique decreases resolution of ADC for keeping conventional readout time [8]. Therefore, all of the pixels will be sampled several times, regardless of the value of those pixel values. Therefore, it has a limitation of effects of multiple sampling because of quantization noise due to large quantization step for achieving larger sampling number. Second, the signal dependent multiple sampling technique has been proposed [9]. It changes its 8sampling number according to pixel values. However, this concept can be achieved after operation of conventional readout. Therefore, it at least doubles readout time compared with conventional one. Finally, conditional multiple sampling technique has been proposed [10]. Similarly, the number of samplings is changed depending on the pixel value. However, it divides into two casesthe bright condition and the dark condition. Therefore, its boundary errors will be significant in output images. The proposed ADC can achieve conserving readout time with using multiple ramp generators. Also, it can change the sampling number according to pixel values gradually without sacrificing resolution of ADC [12]. It is composed with column-level digital logic for ramp selection and ripple local counter then size problem is not critical problem. Therefore, it can reduce boundary errors through the sample counter of the intermediate level. With this concept, adjusting the number of ramp generators, depending on the application, it can take the appropriate sampling number and reduces the power consumption consideration. Therefore, proposed ADC is new concept of signal-dependent multiple sampling technique with several ramp generators without sacrificing ramp resolution and readout time.clos

A Novel Differential Ramp Generator Circuit with PVT Compensation Structure

Applications like counter ADC demanded accurate ramp signal with low power dissipation. This paper presents a novel approach of low power differential ramp generator with negative feedback for the compensation of the variations in process, voltage, and temperature (PVT). The derived equations of the proposed ramp generator circuit show that PVT compensation is enhanced significantly. Additionally, the circuit design and simulations were done in TSMC 0.18-μm CMOS technology. The Monte Carlo simulation results and corner analysis show that the linearity of the ramp signal is about 9-bit while power dissipation of the circuit is about 2.61μW

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

Development of ASIC for SiPM sensor readout

L'abstract è presente nell'allegato / the abstract is in the attachmen

A highly digital microbolometer ROIC employing a novel event-based readout and two-step time to digital converters

Uncooled infrared imaging systems are a light weight and low cost alternative to their cooled counterparts. Uncooled microbolometer IR focal plane arrays (IRFPAs) for applications such as medical imaging, thermography, night vision, surveillance and industrial process control have recently been under focus. These systems have small pixel pitches ( 250 K). Low NETD demands excellent microbolometer and readout noise performance. If sensitive analog circuits, driving long metal interconnects, are part of the predigitization readout channel, this necessitates the use of power consuming buffers, potentially in conjunction with noise cancellation circuits that result in power and area overhead. Thus re-thinking at the architectural level is crucial to meet these demands. Accordingly, in this thesis a column-parallel readout architecture for frame synchronous microbolometer imagers is proposed that enables low power operation by employing a time mode digitizer. The proposed readout circuit is based on a bridge type detector network with active and reference microbolometers and employs a capacitive transimpedance amplifier (CTIA) incorporating a novel two-step integration mechanism. By using a modified reset scheme in the CTIA, a forward ramp is initiated at the input side followed by the conventional backward integrated ramp at the output. This extends the measurement interval and improves signal-to-noise ratio (SNR). A synchronous counter based TDC measures this interval providing robust digitization. This technique also provides a way of compensating for self-heating effects. Being highly digital, the proposed architecture offers robust frontend processing and achieves a per channel power consumption of 66 µW, which is considerably lower than the most recently reported designs, while maintaining better than 10mK readout NETD

CMOS SPAD-based image sensor for single photon counting and time of flight imaging

The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range

Energy Efficient Computing with Time-Based Digital Circuits

University of Minnesota Ph.D. dissertation. May 2019. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); xv, 150 pages.Advancements in semiconductor technology have given the world economical, abundant, and reliable computing resources which have enabled countless breakthroughs in science, medicine, and agriculture which have improved the lives of many. Due to physics, the rate of these advancements is slowing, while the demand for the increasing computing horsepower ever grows. Novel computer architectures that leverage the foundation of conventional systems must become mainstream to continue providing the improved hardware required by engineers, scientists, and governments to innovate. This thesis provides a path forward by introducing multiple time-based computing architectures for a diverse range of applications. Simply put, time-based computing encodes the output of the computation in the time it takes to generate the result. Conventional systems encode this information in voltages across multiple signals; the performance of these systems is tightly coupled to improvements in semiconductor technology. Time-based computing elegantly uses the simplest of components from conventional systems to efficiently compute complex results. Two time-based neuromorphic computing platforms, based on a ring oscillator and a digital delay line, are described. An analog-to-digital converter is designed in the time domain using a beat frequency circuit which is used to record brain activity. A novel path planning architecture, with designs for 2D and 3D routes, is implemented in the time domain. Finally, a machine learning application using time domain inputs enables improved performance of heart rate prediction, biometric identification, and introduces a new method for using machine learning to predict temporal signal sequences. As these innovative architectures are presented, it will become clear the way forward will be increasingly enabled with time-based designs

Digital CMOS ISFET architectures and algorithmic methods for point-of-care diagnostics

Over the past decade, the surge of infectious diseases outbreaks across the globe is redefining how healthcare is provided and delivered to patients, with a clear trend towards distributed diagnosis at the Point-of-Care (PoC). In this context, Ion-Sensitive Field Effect Transistors (ISFETs) fabricated on standard CMOS technology have emerged as a promising solution to achieve a precise, deliverable and inexpensive platform that could be deployed worldwide to provide a rapid diagnosis of infectious diseases. This thesis presents advancements for the future of ISFET-based PoC diagnostic platforms, proposing and implementing a set of hardware and software methodologies to overcome its main challenges and enhance its sensing capabilities. The first part of this thesis focuses on novel hardware architectures that enable direct integration with computational capabilities while providing pixel programmability and adaptability required to overcome pressing challenges on ISFET-based PoC platforms. This section explores oscillator-based ISFET architectures, a set of sensing front-ends that encodes the chemical information on the duty cycle of a PWM signal. Two initial architectures are proposed and fabricated in AMS 0.35um, confirming multiple degrees of programmability and potential for multi-sensing. One of these architectures is optimised to create a dual-sensing pixel capable of sensing both temperature and chemical information on the same spatial point while modulating this information simultaneously on a single waveform. This dual-sensing capability, verified in silico using TSMC 0.18um process, is vital for DNA-based diagnosis where protocols such as LAMP or PCR require precise thermal control. The COVID-19 pandemic highlighted the need for a deliverable diagnosis that perform nucleic acid amplification tests at the PoC, requiring minimal footprint by integrating sensing and computational capabilities. In response to this challenge, a paradigm shift is proposed, advocating for integrating all elements of the portable diagnostic platform under a single piece of silicon, realising a ``Diagnosis-on-a-Chip". This approach is enabled by a novel Digital ISFET Pixel that integrates both ADC and memory with sensing elements on each pixel, enhancing its parallelism. Furthermore, this architecture removes the need for external instrumentation or memories and facilitates its integration with computational capabilities on-chip, such as the proposed ARM Cortex M3 system. These computational capabilities need to be complemented with software methods that enable sensing enhancement and new applications using ISFET arrays. The second part of this thesis is devoted to these methods. Leveraging the programmability capabilities available on oscillator-based architectures, various digital signal processing algorithms are implemented to overcome the most urgent ISFET non-idealities, such as trapped charge, drift and chemical noise. These methods enable fast trapped charge cancellation and enhanced dynamic range through real-time drift compensation, achieving over 36 hours of continuous monitoring without pixel saturation. Furthermore, the recent development of data-driven models and software methods open a wide range of opportunities for ISFET sensing and beyond. In the last section of this thesis, two examples of these opportunities are explored: the optimisation of image compression algorithms on chemical images generated by an ultra-high frame-rate ISFET array; and a proposed paradigm shift on surface Electromyography (sEMG) signals, moving from data-harvesting to information-focused sensing. These examples represent an initial step forward on a journey towards a new generation of miniaturised, precise and efficient sensors for PoC diagnostics.Open Acces