A machine learning system for automated whole-brain seizure detection

Epilepsy is a chronic neurological condition that affects approximately 70 million people worldwide. Characterised by sudden bursts of excess electricity in the brain, manifesting as seizures, epilepsy is still not well understood when compared with other neurological disorders. Seizures often happen unexpectedly and attempting to predict them has been a research topic for the last 30 years. Electroencephalograms have been integral to these studies, as the recordings that they produce can capture the brain’s electrical signals. The diagnosis of epilepsy is usually made by a neurologist, but can be difficult to make in the early stages. Supporting para-clinical evidence obtained from magnetic resonance imaging and electroencephalography may enable clinicians to make a diagnosis of epilepsy and instigate treatment earlier. However, electroencephalogram capture and interpretation is time consuming and can be expensive due to the need for trained specialists to perform the interpretation. Automated detection of correlates of seizure activity generalised across different regions of the brain and across multiple subjects may be a solution. This paper explores this idea further and presents a supervised machine learning approach that classifies seizure and non-seizure records using an open dataset containing 342 records (171 seizures and 171 non-seizures). Our approach posits a new method for generalising seizure detection across different subjects without prior knowledge about the focal point of seizures. Our results show an improvement on existing studies with 88% for sensitivity, 88% for specificity and 93% for the area under the curve, with a 12% global error, using the k-NN classifier

Implantable Asynchronous Epilectic Seizure Detector

RÉSUMÉ Plusieurs algorithmes de détection à faible consommation ont été proposés pour le traitement de l'épilepsie focale. La gestion de l'énergie dans ces microsystèmes est une question importante qui dépend principalement de la charge et de la décharge des capacités parasites des transistors et des courants de court-circuit pendant les commutations. Dans ce mémoire, un détecteur asynchrone de crise pour le traitement de l'épilepsie focale est présenté. Ce système fait partie d'un dispositif implantable intégré pour stopper la propagation de la crise. L'objectif de ce travail est de réduire la dissipation de puissance en évitant les transitions inutiles de signaux grâce à la technique du « clock tree » ; en conséquence, les transistors ne changent pas d'état transitoire dans ce mode d'économie d'énergie (période de surveillance des EEG intracrâniens), sauf si un événement anormal est détecté. Le dispositif intégré proposé comporte un bio-amplificateur en amont (front-end) à faible bruit, un processeur de signal numérique et un détecteur. Un délai variable et quatre détecteurs de fenêtres de tensions variables en parallèles sont utilisés pour extraire de l’information sur le déclenchement des crises. La sensibilité du détecteur est améliorée en optimisant les paramètres variables en fonction des activités de foyers épileptiques de chaque patient lors du début des crises. Le détecteur de crises asynchrone proposé a été implémenté premièrement en tant que prototype sur un circuit imprimé circulaire, ensuite nous l’avons intégré sur une seule puce dans la technologie standard CMOS 0.13μm. La puce fabriquée a été validée in vitro en utilisant un total de 34 enregistrements EEG intracrâniens avec la durée moyenne de chaque enregistrement de 1 min. Parmi ces jeux de données, 15 d’entre eux correspondaient à des enregistrements de crises, tandis que les 19 autres provenaient d’enregistrements variables de patients tels que de brèves crises électriques, des mouvements du corps et des variations durant le sommeil. Le système proposé a réalisé une performance de détection précise avec une sensibilité de 100% et 100% de spécificité pour ces 34 signaux icEEG enregistrés. Le délai de détection moyen était de 13,7 s après le début de la crise, bien avant l'apparition des manifestations cliniques, et une consommation d'énergie de 9 µW a été obtenue à partir d'essais expérimentaux.----------ABSTRACT Several power efficient detection algorithms have been proposed for treatment of focal epilepsy. Power management in these microsystems is an important issue which is mainly dependent on charging and discharging of the parasitic capacitances in transistors and short-circuit currents during switching. In this thesis, an asynchronous seizure detector for treatment of the focal epilepsy is presented. This system is part of an implantable integrated device to block the seizure progression. The objective of this work is reducing the power dissipation by avoiding the unnecessary signal transition and clock tree; as a result, transistors do not change their transient state in power saving mode (icEEG monitoring period) unless an abnormal event detected. The proposed integrated device contains a low noise front-end bioamplifier, a digital signal processor and a detector. A variable time frame and four concurrent variable voltage window detectors are used to extract seizure onset information. The sensitivity of the detector is enhanced by optimizing the variable parameters based on specific electrographic seizure onset activities of each patient. The proposed asynchronous seizure detector was first implemented as a prototype on a PCB and then integrated in standard 0.13 μm CMOS process. The fabricated chip was validated offline using a total of 34 intracranial EEG recordings with the average time duration of 1 min. 15 of these datasets corresponded to seizure activities while the remaining 19 signals were related to variable patient activities such as brief electrical seizures, body movement, and sleep patterns. The proposed system achieved an accurate detection performance with 100% sensitivity and 100 % specificity for these 34 recorded icEEG signals. The average detection delay was 13.7 s after seizure onset, well before the onset of the clinical manifestations. Finally, power consumption of the chip is 9 µW obtained from experimental tests

Simulation and implementation of novel deep learning hardware architectures for resource constrained devices

Corey Lammie designed mixed signal memristive-complementary metal–oxide–semiconductor (CMOS) and field programmable gate arrays (FPGA) hardware architectures, which were used to reduce the power and resource requirements of Deep Learning (DL) systems; both during inference and training. Disruptive design methodologies, such as those explored in this thesis, can be used to facilitate the design of next-generation DL systems

Optimizing AI at the Edge: from network topology design to MCU deployment

The first topic analyzed in the thesis will be Neural Architecture Search (NAS). I will focus on two different tools that I developed, one to optimize the architecture of Temporal Convolutional Networks (TCNs), a convolutional model for time-series processing that has recently emerged, and one to optimize the data precision of tensors inside CNNs. The first NAS proposed explicitly targets the optimization of the most peculiar architectural parameters of TCNs, namely dilation, receptive field, and the number of features in each layer. Note that this is the first NAS that explicitly targets these networks. The second NAS proposed instead focuses on finding the most efficient data format for a target CNN, with the granularity of the layer filter. Note that applying these two NASes in sequence allows an "application designer" to minimize the structure of the neural network employed, minimizing the number of operations or the memory usage of the network. After that, the second topic described is the optimization of neural network deployment on edge devices. Importantly, exploiting edge platforms' scarce resources is critical for NN efficient execution on MCUs. To do so, I will introduce DORY (Deployment Oriented to memoRY) -- an automatic tool to deploy CNNs on low-cost MCUs. DORY, in different steps, can manage different levels of memory inside the MCU automatically, offload the computation workload (i.e., the different layers of a neural network) to dedicated hardware accelerators, and automatically generates ANSI C code that orchestrates off- and on-chip transfers with the computation phases. On top of this, I will introduce two optimized computation libraries that DORY can exploit to deploy TCNs and Transformers on edge efficiently. I conclude the thesis with two different applications on bio-signal analysis, i.e., heart rate tracking and sEMG-based gesture recognition