Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology

Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, thus the temperature coefficient of it is high. Hence, an improved version of piecewise curvature-corrected Bandgap voltage reference circuit which has low voltage variation in wide range of temperature is introduced in this project to overcome the problem mentioned above. The BGR circuit is designed using CMOS compatible process in 0.18μm CMOS process technology and simulated by using Cadence tool. The proposed piecewise curvature-corrected BGR operate properly with output voltage of 558.6 mV to 558.3 mV by varying the voltage supply 1.4 V to 3.3 V at 27°C and the line regulation is 0.016% . Besides that, the best temperature coefficient obtained is 9.2 ppm/°C in the temperature range of -25°C to 150°C at 1.8 V. The PSSR of the proposed circuit is -69.91 dB at frequency less 10 kHz. The layout design of the proposed circuit is done by using Silterra 0.18 μm standard CMOS process and total die area is 0.0175 mm2 and temperature coefficient obtained in post layout simulation is 11.66ppm/°C. In short, it is found that the proposed design of BGR circuit is able to achieve high temperature range and relatively low voltage variation

A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility

Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from −55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420 nA at 27°C

A simple bandgap reference based on VGO extraction with single-temperature trimming

Bandgap references are widely used in analog and mixed-signal systems to provide temperature-independent voltage or current reference. In traditional bandgap structure, the base-emitter voltage VBE of a diode is used to generate a complementary to absolute temperature (CTAT) voltage, which reduces as temperature increases. The base-emitter voltage difference ∆VBE between two diodes with the same current but different emitter areas supplies a proportional to absolute temperature (PTAT) voltage. With the proper adjustment of the coefficients of VBE and ∆VBE in a voltage summer, the temperature dependency of the summed voltage can be mostly canceled out and the output voltage can achieve a relative temperature-constant property. However, even though the linear terms of temperature-dependent components in PTAT and CTAT expressions can be canceled out, there are still some high order terms left, which still affect temperature dependency. For this reason, a first-order bandgap reference with only PTAT and CTAT linear term compensation cannot achieve a sufficiently low temperature coefficient (TC), normally ranging from 10ppm/°C to over 100ppm/°C. To achieve higher precision and lower TC, the high order terms also need to be considered and compensated by some techniques. This thesis study describes the development of a high order bandgap structure, including the initial thinking, design flow, equation derivation, circuit implementation, and simulation result

Very low thermal drift precision virtual voltage reference

A digital-based, process-supply-and-temperature independent voltage reference suitable to nanoscale CMOS technologies, which exploits the recently proposed ‘virtual reference’ concept to achieve a very low thermal drift, is presented. Its performance is assessed on the basis of simulations and experiments carried out on a microcontroller-based, proof-of-concept prototype and is compared with state-of-the-art integrated analogue and digital voltage references. A simulated (measured) thermal drift as low as 1 ppm/°C (5 ppm/°C) in the temperature range −40/+140°C (−10/+100°C) is reported

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

Low Power, High PSR CMOS Voltage References

With integration of various functional modules such as radio frequency (RF) circuits, power management, and high frequency digital and analog circuits into one system on chip (SoC) in recent applications, power supply noise can cause significant system performance deterioration. This makes supply noise rejection of the embedded voltage reference crucial in modern SoC applications. Also the use of resistors in bandgap voltage references makes them less suitable for modern low power and portable applications. This thesis introduces two resistorless sub-1 V, all MOSFET references. The goal is to achieve a high power supply rejection (PSR) over a wide bandwidth not achieved in previous works. This high PSR over wide bandwidth is achieved by using a combination of a feedback technique and an innovative compact MOSFET low pass filter. The two references were fabricated in a standard 0.18 µm CMOS process. The first reference uses a composite transistor in subthreshold to produce a proportional-to-absolute temperature (PTAT) voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The second references uses dynamic-threshold voltage MOSFET (DTMOS) to produce a PTAT voltage which is converted to a current used to thermally compensate the threshold voltage of a MOSFET in saturation. The measurement shows that both references consumes a sub-1 µW power across their entire operating temperatures. The first reference achieves a PSR better than 50 dB for frequencies of up to 70 MHz and a 20 ppm/°C temperature coefficient (TC) for temperatures from -35 °C — 80 °C. It has a compact area of 0.0180 mm2 and operates on a supply of 1.2 V — 2.3 V. The second reference achieves a PSR better than 50 dB for frequencies of up to 60 MHz. This reference achieves a TC of 9.33 ppm/°C after trimming for temperatures from -30 °C — 110 °C and a line regulation of 0.076 %/V for a step from 0.8 V to 2 V supply voltage with 360 nW power consumption at room temperature. It has a compact area of 0.0143 mm^2

Fully Integrated Voltage Reference Circuits

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2014(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2014Gerilim referans devreleri, elektriksel sistemlerde diğer alt blokların çalışmaları için kararlı bir çalışma noktası üretmeleri sebebiyle veri dönüştürücüler (ADC - DAC), frekans sentezleyiciler, DC-DC ve AC-DC dönüştürücüler ve lineer regülatörler gibi pek çok elektriksel sistemin en temel yapı bloklarındandır. İdeal olarak, üretilen bu referans noktası, sıcaklık, üretim süreçleri, besleme gerilim degişimleri ve yükleme etkileri gibi çalışma koşullarından etkilenmemelidir. Bir referans devresinin doğruluğu bahsedilen çalışma koşullarının etkisiyle mutlak değerinden ne kadar saptığı olarak tanımlanır. Modern haberleşme sistemleri ve tüketici ürünlerindeki gelişmeler ile birlikte yüksek entegrasyon ve doğruluklu sistemlere olan talep artmıştır. Tümdevre sistemlerinde, alt blokların çalışma noktalarını belirlemesi nedeniyle özellikle referans devrelerinin performansları bütün sistemin performansının belirlenmesinde önemli rol oynamaktadır. Dolayısıyla yüksek performanslı sistemlere olan talep, bu performansların elde edilmesi için kullanılan düşük geometrili üretim teknolojilerine uygun, yani giderek azalan besleme gerilimleri ile çalışabilecek yüksek doğruluklu referans devrelerine olan talebi de arttırmıştır. Bu nedenle bu çalışmada gerilim referans devre topolojilerine odaklanılmıştır. Bu doğrultuda, öncelikle yüksek doğruluklu, düşük gürültülü gerilim refereans devre topolojileri üzerinde çalışılarak 0.35 um CMOS teknoljisinde farklı tasarımlar yapılmıştır. Bu aşamada temel hedef, yüksek dogrulukluk olarak belirenmiş ve yapılan tasarımlarda, üretim sonrası ayarlamalardan sonra sıcaklık katsayısı 3 ppm/C olabilecek devreler tasarlanmıştır. Ancak, 0.35 um CMOS üretim teknolojisi kullanılması ve kullanılan topolojiler dolayısıyla, devrelerin çalışabileceği minimum besleme gerilim seviyesi 1.8 V ile sınırlı kalmıştır. Devrelerin çektikleri akımlar ise 20-30 uA seviyesindedir. Bu tasarımlar sırasında (triple-well üretim teknlojileri için), önerilen blok gövde izolasyon stratejisi, tasarımı yapılan devrenin gövdesinin tümdevrenin geri kalan kısmından ters kutuplanmış bir jonksiyon diyodu sayesinde izole edilmesine dayanmaktadır ve devrenin gövde gürültüsünden etkilenmesini önemli ölçüde azaltmaktadır. Son olarak, çoğunlukla osilatör devrelerinde uygulanan anahtarlamalı kutuplama tekniği uygulanarak devrelerin düşük frekans gürültü performansının iyileştirilmesi amaçlanmıştır. Çalışmanın geri kalan kısmında, düşük besleme gerilimleriyle çalışabilecek mikron-altı üretim teknolojilerine uygun gerilim referans devre topolojileri üzerine odaklanılmıştır. Bu doğrultuda, iki yeni düşük besleme gerilimli ve düşük güç tüketimli gerilim referans devre topolojisi önerilmiştir. Önerilen topolojiler, 0.18 um CMOS üretim teknolojisinde gerçeklenmiştir. Ölçüm sonuçları, tasarlanan gerilim refarans devrelerinin 0.65 V besleme gerilimi ile çalışabildiğini göstermiştir. Önerilen devre topolojileri ile 0-120 C sıcaklık aralığında, sıcaklık katsayısı 50 ppm/C olan 193 mV seviyesinde referans gerilimleri elde edilmiştir. Devrelerin güç tüketimleri sırasıyla 0.3 uW ve 0.4 uW iken kapladıkları alan 0.2 mm^2 ve 0.08 mm^2 dir. Sonuç olarak, önerilen devre topolojileri ile literatürde yer alan diğer 1V-altı referans devreleri ile karşılatrılabilir seviyede sıcaklık katsayısı olan referans gerilimleri çok daha düşük güç harcamasıyla elde edilmiştir.Voltage references are one of the basic building blocks of many SoCs and mixed-signal ICs such as data converters, voltage regulators and operational amplifiers as they constitute a stable reference voltage for other sub-circuits to generate predictable and repeatable results. Ideally, this reference point should not change with external influences or operating conditions such as temperature, fabrication process variations, power supply variations and transient loading effects. Along with the rapid development of modern communication systems and consumer products, which constitutes the main market for semiconductor industry, the market demand for these System on Chip (SoC) or Mixed Signal ICs to have lower power consumption, higher accuracy and lower cost, and thus, higher integration. Since the performance of the whole system depends strongly to the performance of the reference circuit, this work is focused on fully integrated voltage reference architectures. With this motivation, firstly, different kinds of high precision low noise voltage reference circuits are designed in standard 0.35 um CMOS technology that we have more experience and knowledge of. The essential goal of these studies was high precision and temperature coefficient of the designed voltage reference circuits are on the order of 3 ppm/C with trimming after production. However, since 0.35 um CMOS technology is used in these designs and also due to the chosen topologies their minimum supply voltage can be down to 1.8 V and while current consumption is on the order of 20-30 uA. In the design of the this voltage reference block bulk isolation technique is proposed (for triple-well CMOS processes), in which system blocks are bulk isolated by a reverse biased junction diode from the rest of the die to drastically reduce substrate noise coupling. This is especially important if a very low power voltage reference is designed in a very noisy SoC. Moreover, the switched biasing technique, which is mostly applied to the oscillators, is also implemented to the designed BGR in order to improve the low noise performance of the circuit. The rest of the thesis is focused on new voltage reference topologies that are appropriate for sub-micron technologies operating with low supply voltages. With this motivation two new low voltage and low power voltage reference topologies are proposed. The proposed voltage reference topologies are implemented and fabricated in 0.18 um CMOS technology. Measurement results show that the proposed voltage reference circuits are working properly down to 0.65 V and achieve an output voltage of 193 mV with a temperature coefficient on the order of 50 ppm/C in the temperature range of 0-120C. The total power consumption of the two designed voltage references are 0.3 uW and 0.4 uW at 27 C, while occupying the area of 0.2 mm^2 and 0.08 mm^2, respectively. As a result, the proposed voltage reference topologies generate a reference voltage with comparable level of temperature coefficient and quite low power consumption with respect to the other sub-1V voltage reference circuits reported in the literature.DoktoraPh

Low temperature coefficient bandgap voltage reference generator

The maximum achievable performance of almost all mixed-signal and radio frequency systems is dependent on the accuracy of voltage references. The bandgap voltage of silicon at zero Kelvin, VGO is a physical constant with unit Volts. It is independent of process, supply voltage and temperature variations. This work proposes a strategy for extracting VGO and expressing it at the output of a voltage reference circuit. The concept is implemented in UMC 65nm process and the simulation results indicate that the circuit design can achieve very low temperature coefficients (\u3c1ppm/°C). The proposed concept is validated using measurements and the associated constraints are carefully investigated. The measured output voltage reference of the two tested units record a temperature coefficient of 3.4ppm/°C and 4.57ppm/°C across the industrial temperature range (-40°C to 85°C)

A low noise, sub-1ppm/oC piecewise second-order curvature compensated bandgap reference for high resolution ADC

학위논문 (석사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김수환.본 논문에서는 고해상도 analog to digital converter를 위한 저 잡음, 고 정밀 bandgap voltage reference를 제안한다. reference 회로의 성능 중 가장 중요한 것들은 바로 낮은 온도 계수(temperature coefficient)와 저주파 대역의 전기적 잡음이다. 제안된 Bandgap reference 회로는 위 두가지 요소를 개선 하였다. 먼저 낮은 온도 계수를 성취하기 위해서는 BJT Emitter-Base전압의 비선형적 온도의존성을 보상해주어야 하고, bandgap core을 이루는 Error amplifier의 DC offset을 제거해야 하며, 마지막으로 process variation에의한 추가적인 온도 의존성을 상쇄시켜야 한다. 제안된 bandgap reference는 여러가지 회로 기술들을 활용해 위 요소들을 보상하였다. BJT Emitter-Base전압의 비선형적 온도 의존성을 온도에 대해 2차 의존성을 갖는 compensation 전류를 생성하고 bandgap core에 흘려주어 제거하였다. Compensation 전류는 크게 current subtraction 동작과 current squaring 동작을 통해 생성되는데, 위 동작은 모두 process variation에 둔감하다. 두 번 째로 process variation에 의한 온도 특성의 변화를 보상해 주기 위해 trimming resistor를 사용하였다. 마지막으로 error amplifier에 chopping을 적용하여 Error amplifier DC offset을 약화시켰다. Bandgap reference의 저 주파수 전기적 잡음의 근원은 대부분 Error amplifier이므로 chopping 동작을 통해 저주파대역의 전기적 잡음 또한 제거된다. Chopping 동작을 통해 생겨난 리플 과, 고주파 대역으로 변조된 저주파 대역의 전기적 잡음은 RC filter를 통해 제거하였다. 제안된 bandgap reference는 스탠다드 0.13um CMOS 공정의 3.3V 전원 소자로 설계하였으며 레이아웃 사이즈는 0.0534mm2이다. Post layout simulation 결과 제안된 bandgap reference의 -40°C부터 125°C 사이의 온도 계수는 약 0.64ppm/°C이다. 0.1Hz부터 10Hz사이의 integrated noise는 약 2.7uVrms이다. 제안된 bandgap reference는 상온에서 약 44uA의 전류를 소모한다.In this thesis a low noise and high precision bandgap reference is presented. One of the most important characteristics of reference circuit for analog to digital converter with high resolution is low temperature drift and low noise. The proposed bandgap reference improves these two characteristics. To achieve low temperature coefficient(TC), non-linear temperature dependence of emitter-base voltage of bipolar transistor should be compensated. Also, degradation of TC due to dc offset of the error amplifier and process variation is another concern. The proposed bandgap reference compensates these factors by utilizing various circuit technique. Because non-linear temperature dependence of bipolar transistor has a concave shape with temperature, second order curvature compensation current is generated by using current subtraction circuit and current squaring circuit and injected into bandgap core. The current subtraction and squaring operation is tolerant to process variation. To achieve low temperature coefficient regardless of process variation, PTAT trimming is utilized to compensate added linear temperature dependence. At last, to remove dc offset of the error amplifier, chopping technique is applied to the error amplifier. Ripple and up-modulated low frequency caused by chopping operation is removed through RC-filter. The proposed bandgap reference is designed in 0.13um standard CMOS process. Layout size of the bandgap reference is 0.0534mm2. Post layout simulation shows that TC of the bandgap reference from -40°C to 125 °C is 0.64ppm/°C. In addition, integrated noise from 0.1Hz to 10Hz is about 2.7uVrms. The proposed bandgap reference consumes 44uA at room temperature제 1 장 서론 1 제 1 절 연구의 배경 1 제 2 절 기본적인 bandgap reference의 동작 원리. 4 1. bipolar 트랜지스터의 온도 특성 4 2. 기본적인 bandgap voltage reference의 동작 원리 7 3. 기본적인 bandgap current reference의 동작 원리 9 제 2 장 기본적인 bandgap reference의 성능적 한계 12 제 1 절 비선형적 온도 의존성 12 1. error amplifier dc offset 14 2. emitter-base 전압의 비선형적 온도 의존성 16 3. bipolar 트랜지스터 전류 이득에 의한 비선형적 온도 의존성 17 4. bipolar 트랜지스터의 베이스 저항에 의한 비선형적 온도 의존성 19 제 2 절 Bandgap reference의 전기적 잡음. 20 제 3 장 제안하는 저 잡음 고 정밀 bandgap voltage reference 22 제 1절 제안된 bandgap reference의 전체 구조 22 1. PTAT전류 생성 회로 23 2. reference 전류 생성 회로 24 3. bandgap core 25 제 2절 Curvature compensation technique 25 제 3절 Noise reduction technique 30 제 4절 Resistor trimming 32 제 5절 주요 성분 파라 미터 테이블 33 제 4 장 Layout 및 모의 실험 결과 34 제 1 절 Layout 34 제 2 절 모의 실험 결과 35 제 5 장 결론 40 제 6 장 부록 current squaring 회로의 동작 원리. 41 참고문헌 43 Abstract 43Maste

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature