A 0.3-1.2V Schottky-Based CMOS ZTC Voltage Reference

A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3V up to 1.2V and outputs three different reference voltages using Standard-VT (SVT), Low-VT (LVT), and Zero-VT (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13-µm CMOS process show a worst-case normalized standard deviation (σ/µ) of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TCeff) range from 140 to 200 ppm/oC over the full commercial temperature range. At room temperature (25oC), line sensitivity in the ZVT VR is just 1.3%/100mV, over the whole supply range. The proposed reference draws around 5 µW and occupies 0.014 mm2 of silicon area

MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

集積化AlGaN/GaNイオン感応性電界効果トランジスタに関する研究

AlGaN/GaN heterostructure ion-sensitive field-effect transistors (ISFETs) can provide high sensitivity and fast response due to the high electron mobility and high electron density providing by the two-dimensional electron gas (2DEG) generated at the AlGaN/GaN heterostructure interface. My research mainly focuses on the investigation of the integrated AlGaN/GaN ISFETs for pH sensing. To achieve high performance on AlGaN/GaN ISFET pH sensor, we fabricated sensors with different Al composition (25%, and 35%). We compared the characteristics of the sensors with 25% and 35% Al composition. The pH sensor with Al composition (35%) in the barrier layer with a 16 nm transition layer of 25% Al composition shows better surface sensitivity (SV) of 56.01 mV/pH, which is higher than that of the sensor with 25% Al composition (53.94 mV /pH), but worse current sensitivity SA (-0.095 mA/pH Vs -0.102 mA/pH). In addition, threshold voltage increases from approximately -1.6 V to approximately -0.8 V when measured in alkaline solution for 5 times, along with a decreasing output current. High-resolution SEM photos show that there are high density hexagonal pits with the size of approximately 100 nm on the device surface, presenting the etching effect along the dislocations during alkaline sensing. The X-ray photoelectron spectroscopy (XPS) demonstrates that the intensity of the Ga3d and Al2p spectra decreases after pH sensing measurement, implying the variation of chemical component occurs in the upper AlGaN thin layer. Many voids with a size of approximately 100 nm were observed from the transmission electron microscope (TEM) pictures, which are comparable with that of the scanning electron microscope (SEM). Combining with the energy dispersive X-ray spectroscopy (EDX), the degradation in electrical performance can be attributed to the transformation of AlGaN into oxide as well as the followed alkaline solution dissolve. To avoid the reaction of surface Al with solution, a 3 nm GaN cap layer was added. To reduce the barrier layer thickness, a recessed gate with a length of 2 μm and a depth of about 14 nm was formed. The current sensitivity of the AlGaN/GaN ISFET pH sensors has been improved by 61%, from 52.25 to 84.39 μA/pH, by the recessed-gate structure and ammoniate water treatment. A pH meter system based on the GaN pH sensor was constructed and evaluated. GaN-based ISFET can measure the pH value of the solutions with similar circuit, whether in the linear region or the saturation region. The measurement is stable and repeatable. The small current in the linear region can make the measurement stable and fast, but the resolution is a bit low. High resolution can be obtained in the saturation region, but the measurement is unstable due to excessive current. The Schottky barrier diode (SBD) based on GaN can be used for temperature sensing, and the temperature sensitivity can be improved by different structure design. A recessed anode AlGaN/GaN SBD is suitable to integrate with GaN-based power device for temperature sensor application. The temperature dependent forward voltage at a fixed current shows good linearity, resulting in a sensitivity of approximately 1.0 mV/K. The p-NiO guard ring can suppress the electric field at the anode/GaN interface and field crowding at the anode edge effectively, which enhances the breakdown voltage to approximately -250 V. Using the same material, we can design an integrated device sensor based on GaN to measure temperature and pH simultaneously, which will solve the measurement deviation of pH sensor at different temperatures

Estudio del diseño de un circuito de voltaje de referencia para aplicaciones de bajo voltaje y bajo consumo de energía

Este trabajo de investigación describe el funcionamiento de los circuitos que permiten la generación de un voltaje de referencia estable ante variaciones en la temperatura y el voltaje de alimentación. Las topologías clásicas de circuitos de voltaje de referencia limitan el voltaje que entregan a valores cercanos a 1.2 V, impidiendo que aplicaciones de menor voltaje puedan hacer uso de dichos circuitos. El principal inconveniente yace en que las topologías clásicas de estos circuitos limitan el voltaje que entregan a valores cercanos a 1.2 V. Actualmente muchos circuitos integrados se diseñan para operar con voltajes menores a 1.2 V, de modo que es necesario plantear las consideraciones que permitan el diseño de un circuito de voltaje de referencia de bajo voltaje. El propósito de este trabajo de investigación es exponer los fundamentos para el diseño de un circuito de voltaje de referencia. Se desarrolla la teoría que permite la obtención de un voltaje independiente de la temperatura. Posteriormente se analizan dos topologías: una convencional y otra de bajo voltaje. Esta última sirve de referencia para el diseño de voltaje de referencia de bajo voltaje. En la parte final de esta investigación se enuncian conclusiones sobre el marco teórico revisado. También se mencionan recomendaciones para el diseño de un circuito de bajo voltaje.Trabajo de investigació

Temperature sensors in SOI CMOS for high temperature applications

Ph.DDOCTOR OF PHILOSOPH

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Diamond Schottky barrier diodes

Research on wide band gap semiconductors suitable for power electronic devices has spread rapidly in the last decade. The remarkable results exhibited by silicon carbide (SiC) Schottky batTier diodes (SBDs), commercially available since 2001, showed the potential of wide band gap semiconductors for replacing silicon (Si) in the range of medium to high voltage applications, where high frequency operation is required. With superior physical and electrical properties, diamond became a potential competitor to SiC soon after Element Six reported in 2002 the successful synthesis of single crystal plasma deposited diamond with high catTier mobility. This thesis discusses the remarkable properties of diamond and introduces several device structures suitable for power electronics. The calculation of several figures of merit emphasize the advantages of diamond with respect to silicon and other wide band gap semiconductors and clearly identifies the areas where its impact would be most significant. Information regarding the first synthesis of diamond, which took place back in 1954, together with data regarding the modern technological process which leads nowadays to high-quality diamond crystals suitable for electronic devices, are reviewed. Models regarding the incomplete ionization of atomic dopants and the variation of catTier mobility with doping level and temperature have been elaborated and included in numerical simulators. The study introduces the novel diamond M-i-P Schottky diode, a version of power Schottky diode which takes advantage of the extremely high intrinsic hole mobility. The structure overcomes the drawback induced by the high activation energies of acceptor dopants in diamond which yield poor hole concentration at room temperature. The complex shape of the on-state characteristic exhibited by diamond M-i-P Schottky structures is thoroughly investigated by means of experimental results, numerical simulations and theoretical considerations. The fabrication of a ramp oxide termination on a diamond device is for the first time reported in this thesis. Both experimental and simulated results show the potential of this termination structure, previously built on Si and SiC power devices. A comprehensive comparison between the ramp oxide and two other versions of the field plate termination concept, the single step and the three-step structures, has been performed, considering aspects such as electrical performance, occupied area, complexity of technological process and cost. Based on experimental results presented in this study, together with predictions made via simulations and theoretical models, it is concluded that diamond M-i-P Schottky diodes have the ability to deliver significantly higher performance compared to that of SiC SBDs if issues such as material defects, Schottky contact formation and measurement of reliable ionization coefficients are carefully addressed in the near future

A fully-integrated 180 nm CMOS 1.2 V low-dropout regulator for low-power portable applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a -40 to 120 degrees C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (I-q = 8.6 mu A) and minimum area consumption (0.109 mm(2)) are maintained, including a reference voltage V-ref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off

Design of a reliability methodology: Modelling the influence of temperature on gate Oxide reliability

An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models. Each model is based on a physics of failure approach and includes on the effects of temperature. At all stages the models are verified experimentally on modern deep sub-micron devices. The research provides the foundations of a tool which gives the user the opportunity to make appropriate trade-offs between performance and reliability, and that can be implemented in the early stages of product development