Ball lens embedded through-package via to enable backside coupling between silicon photonics interposer and board-level interconnects

Development of an efficient and densely integrated optical coupling interface for silicon photonics based board-level optical interconnects is one of the key challenges in the domain of 2.5D/3D electro-optic integration. Enabling high-speed on-chip electro-optic conversion and efficient optical transmission across package/board-level short-reach interconnections can help overcome the limitations of a conventional electrical I/O in terms of bandwidth density and power consumption in a high-performance computing environment. In this context, we have demonstrated a novel optical coupling interface to integrate silicon photonics with board-level optical interconnects. We show that by integrating a ball lens in a via drilled in an organic package substrate, the optical beam diffracted from a downward directionality grating on a photonics chip can be coupled to a board-level polymer multimode waveguide with a good alignment tolerance. A key result from the experiment was a 14 chip-to-package 1-dB lateral alignment tolerance for coupling into a polymer waveguide with a cross-section of 20 x 25. An in-depth analysis of loss distribution across several interfaces was done and a -3.4 dB coupling efficiency was measured between the optical interface comprising of output grating, ball lens and polymer waveguide. Furthermore, it is shown that an efficiency better than -2 dB can be achieved by tweaking few parameters in the coupling interface. The fabrication of the optical interfaces and related measurements are reported and verified with simulation results

VCSEL Cavity Engineering for High Speed Modulation and Silicon Photonics Integration

The GaAs-based vertical-cavity surface-emitting laser (VCSEL) is the standard light source in today\u27s optical interconnects, due to its energy efficiency, low cost, and high speed already at low drive currents. The latest commercial VCSELs operate at data rates of up to 28 Gb/s, but it is expected that higher speeds will be required in the near future.One important parameter for the speed is the damping of the relaxation oscillations. A higher damping is affordable at low data rates to reduce signal degradation due to overshoot and jitter, while lower damping is required to reach higher data rates. A VCSEL with the damping optimized for high data rates enabled error-free transmission at record-high data rates up to 57 Gb/s.For future interconnect links it is of interest with tighter integration between the optics and the silicon-based electronics. Techniques to heterogeneously integrate GaAs-based VCSELs on silicon could potentially enable integrated multi-wavelength VCSEL arrays, thus increasing the data rate through wavelength division multiplexing. Heterogeneous integration of GaAs-based VCSELs would also benefit applications that need short-wavelength light sources, such as photonic integrated circuits for life sciences and bio photonics. Silicon-integrated short-wavelength hybrid-cavity VCSELs with up to 2.3 mW optical output power and 12 GHz modulation bandwidth, which enables data transmission at up to 25 Gb/s, are demonstrated by employing ultra-thin adhesive bonding. Further, a vertical-cavity silicon-integrated laser (VCSIL) with in-plane waveguide emission is demonstrated by employing an intra-cavity waveguide with a weak diffraction grating that couples light from the standing wave in the vertical cavity into an in-plane waveguide

4-channel 200 Gb/s WDM O-band silicon photonic transceiver sub-assembly

We demonstrate a 200G capable WDM O-band optical transceiver comprising a 4-element array of Silicon Photonics ring modulators (RM) and Ge photodiodes (PD) co-packaged with a SiGe BiCMOS integrated driver and a SiGe transimpedance amplifier (TIA) chip. A 4 x 50 Gb/s data modulation experiment revealed an average extinction ratio (ER) of 3.17 dB, with the transmitter exhibiting a total energy efficiency of 2 pJ/bit. Data reception has been experimentally validated at 50 Gb/s per lane, achieving an interpolated 10E-12 bit error rate (BER) for an input optical modulation amplitude (OMA) of -9.5 dBm and a power efficiency of 2.2 pJ/bit, yielding a total power efficiency of 4.2 pJ/bit for the transceiver, including heater tuning requirements. This electro-optic subassembly provides the highest aggregate data-rate among O-band RM-based silicon photonic transceiver implementations, highlighting its potential for next generation WDM Ethernet transceivers. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

50 GBd PAM4 transmitter with a 55nm SiGe BiCMOS driver and silicon photonic segmented MZM

We demonstrate an optical transmitter consisting of a limiting SiGe BiCMOS driver co-designed and co-packaged with a silicon photonic segmented traveling-wave Mach-Zehnder modulator (MZM). The MZM is split into two traveling-wave segments to increase the bandwidth and to allow a 2-bit DAC functionality. Two limiting driver channels are used to drive these segments, allowing both NRZ and PAM4 signal generation in the optical domain. The voltage swing as well as the peaking of the driver output are tunable, hence the PAM4 signal levels can be tuned and possible bandwidth limitations of the MZM segments can be partially alleviated. Generation of 50 Gbaud and 53 Gbaud PAM4 yields a TDECQ of 2.8 and 3.8 dB with a power efficiency of 3.9 and 3.6 pJ/bit, respectively; this is the best reported efficiency for co-packaged silicon transmitters for short-reach datacenter interconnects at these data rates. With this work, we show the potential of limiting drivers and segmented traveling-wave modulators in 400G capable short-reach optical interconnects

Wafer-level vacuum sealing for packaging of silicon photonic MEMS

Silicon (Si) photonic micro-electro-mechanical systems (MEMS), with its low-power phase shifters and tunable couplers, is emerging as a promising technology for large-scale reconfigurable photonics with potential applications for example in photonic accelerators for artificial intelligence (AI) workloads. For silicon photonic MEMS devices, hermetic/vacuum packaging is crucial to the performance and longevity, and to protect the photonic devices from contamination. Here, we demonstrate a wafer-level vacuum packaging approach to hermetically seal Si photonic MEMS wafers produced in the iSiPP50G Si photonics foundry platform of IMEC. The packaging approach consists of transfer bonding and sealing the silicon photonic MEMS devices with 30 μm-thick Si caps, which were prefabricated on a 100 mm-diameter silicon-on-insulator (SOI) wafer. The packaging process achieved successful wafer-scale vacuum sealing of various photonic devices. The functionality of photonic MEMS after the hermetic/vacuum packaging was confirmed. Thus, the demonstrated thin Si cap packaging shows the possibility of a novel vacuum sealing method for MEMS integrated in standard Si photonics platforms