A current-driven six-channel potentiostat for rapid performance characterization of microbial electrolysis cells

Knowledge of the performance of microbial electrolysis cells under a wide range of operating conditions is crucial to achieve high production efficiencies. Characterizing this performance in an experiment, however, is challenging due to either the long measurement times of steady-state procedures or the transient errors of dynamic procedures. Moreover, wide parallelization of the measurements is not feasible due to the high measurement equipment cost per channel. Hence, to speedup this characterization and to facilitate low-cost, yet widely parallel measurements, this paper presents a novel rapid polarization curve measurement procedure with a dynamic measurement resolution that runs on a custom six-channel potentiostat with a current-driven topology. As case study, the procedure is used to rapidly assess the impact of altering pH values on a microbial electrolysis cell that produces H-2. A $\times 2$ - $\times 12$ speedup could be obtained in comparison with the state-of-the-art, depending on the characterization resolution (16-128 levels). On top of this speedup, measurements can be parallelized up to $6\times$ on the presented, affordable-42-per-channel-potentiostat

VLSI Implementation of TDC Architectures Used in PET Imaging Systems

Positron emission tomography (PET) is a medical imaging method based on the measurement of concentrations of positron-emitting radionuclides in a living body. In the PET imaging system, glucose is labeled with a positron-emitting radionuclide and injected intravenously. Then, the positrons move through the tissue and collide with the electrons of the cells in which they interact. As a result of this interaction, two gamma rays are emitted in the opposite direction. Gama rays emitted from cancerous tissue that has retained radioactive glucose are detected through ring-shaped detectors. And the detected signals are converted into an electrical response. Subsequently, these responses are sampled with electronic circuits and recorded as histogram matrix to generate the image set. The gamma rays may not reach the detectors located in the opposite position in equal time. In PETs having TOF characteristics, it is aimed to obtain better positioning information by a method based on the principle of measuring the difference between the reach time of the two photons to detectors. The measurement of the flight time is carried out with TDC structures. The measurement of this time difference at the ps level is directly related to the spatial resolution of the PET system. In this study, 45 nm CMOS VLSI simulations of TDC structures that have various architectural approaches were performed for use in PET systems. With the designed TDC architectures, two gamma photons time reach to detectors have been simulated and the time difference has been successfully digitized. In addition, various performance metrics such as input and output voltages, time resolutions, measurement ranges, and power analysis of TDC architectures have been determined. Proposed Vernier oscillator-based TDC architecture has been reached 25 ps time resolution with a low power consumption of 1.62681 mW at 1V supply voltage.Comment: 8 pages, in Turkish language. 6 figures, conference paper,International Marmara Sciences Congess (IMASCON 2019 SPRING), https://www.imascon.com/dosyalar/imascon2019bahar/imascon_fen_bildiriler_ciltII_bahar_2019.pdf , https://avesis.kocaeli.edu.tr/yayin/99073ee1-45ff-495e-9cab-42de4d0fad71/vlsi-implementation-of-tdc-architectures-used-in-pet-imaging-system

MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2 . The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption. Keywords: TDC; time-to-digital converter; fast timing; PET; VLSI; ASIC; ToF; ToT; low power; frontend electronic

Efficient offline outer/inner DAC mismatch calibration in wideband ΔΣ ADCs

Distortion due to feedback DAC mismatch is a key limitation in Delta Sigma ADCs for wideband wireless communications. This article presents an efficient frequency-domain mask-based offline mismatch calibration method of both the outer DAC and the inner DACs in a Delta Sigma ADC. The test stimulus for the calibration is a two-tone signal near the band edge. To avoid the need for high-performance signal generation, a frequency mask is applied to void the stimulus signal and its phase noise. In this way, the method is robust against distortion and jitter in the stimulus signal, which therefore could be combined from two low-quality signal generators. The two-tone band-edge signal has the additional benefit that the number of needed samples of the excitation signal is very modest because as many intermodulations as possible contribute to the calculation of the mismatch errors of the DACs. Experimental results confirming the calibration method are obtained from a prototype chip, designed for an 85MHz signal bandwidth in 28nm CMOS technology. A two-tone stimulus around 78 MHz is applied to calculate the mismatch of the outer DAC and the inner DAC with only 68K samples. With the DACs calibrated, an SFDR improvement of 28.1 dB is achieved for a single-tone input at 5 MHz, while for a two-tone input around 71 MHz, the IM3 is improved from -63.6 dBc to below the noise floor (<-94.1 dBc). This illustrates the effectiveness of the approach

Axp: A hw-sw co-design pipeline for energy-efficient approximated convnets via associative matching

The reduction in energy consumption is key for deep neural networks (DNNs) to ensure usability and reliability, whether they are deployed on low-power end-nodes with limited resources or high-performance platforms that serve large pools of users. Leveraging the over-parametrization shown by many DNN models, convolutional neural networks (ConvNets) in particular, energy efficiency can be improved substantially preserving the model accuracy. The solution proposed in this work exploits the intrinsic redundancy of ConvNets to maximize the reuse of partial arithmetic results during the inference stages. Specifically, the weight-set of a given ConvNet is discretized through a clustering procedure such that the largest possible number of inner multiplications fall into predefined bins; this allows an off-line computation of the most frequent results, which in turn can be stored locally and retrieved when needed during the forward pass. Such a reuse mechanism leads to remarkable energy savings with the aid of a custom processing element (PE) that integrates an associative memory with a standard floating-point unit (FPU). Moreover, the adoption of an approximate associative rule based on a partial bit-match increases the hit rate over the pre-computed results, maximizing the energy reduction even further. Results collected on a set of ConvNets trained for computer vision and speech processing tasks reveal that the proposed associative-based hw-sw co-design achieves up to 77% in energy savings with less than 1% in accuracy loss

A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V

A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA

An Imaged-Based Method for Universal Performance Evaluation of Electrical Impedance Tomography Systems

This paper describes a simple and reproducible methodology for universal evaluation of the performance of electrical impedance tomography (EIT) systems using reconstructed images. Based on objective full referencing (FR), the method provides a visually distinguishable hot colormap and two new FR metrics, the global and the more specific region of interest, to address the issues where common electrical parameters are not directly related to the quality of EIT images. A passive 16 electrode EIT system using an application specific integrated circuit front-end was used to evaluate the proposed method. The measured results show, both visually and in terms of the proposed FR metrics, the impact on recorded EIT images with different design parameters and non-idealities. The paper also compares the image results of a passive electrode system with a matched single variable active electrode system and demonstrates the merit of an active electrode system for noise interference

Sequence-To-Sequence Neural Networks Inference on Embedded Processors Using Dynamic Beam Search

Sequence-to-sequence deep neural networks have become the state of the art for a variety of machine learning applications, ranging from neural machine translation (NMT) to speech recognition. Many mobile and Internet of Things (IoT) applications would benefit from the ability of performing sequence-to-sequence inference directly in embedded devices, thereby reducing the amount of raw data transmitted to the cloud, and obtaining benefits in terms of response latency, energy consumption and security. However, due to the high computational complexity of these models, specific optimization techniques are needed to achieve acceptable performance and energy consumption on single-core embedded processors. In this paper, we present a new optimization technique called dynamic beam search, in which the inference complexity is tuned to the difficulty of the processed input sequence at runtime. Results based on measurements on a real embedded device, and on three state-of-the-art deep learning models, show that our method is able to reduce the inference time and energy by up to 25% without loss of accuracy