Determining EMIC Wave Vector Properties Through Multi-Point Measurements: The Wave Curl Analysis

Electromagnetic ion cyclotron (EMIC) waves play important roles in particle loss processes in the magnetosphere. Determining the evolution of EMIC waves as they propagate and how this evolution affects wave-particle interactions requires accurate knowledge of the wave vector, k. We present a technique using the curl of the wave magnetic field to determine k observationally, enabled by the unique configuration and instrumentation of the Magnetospheric MultiScale (MMS) spacecraft. The wave curl analysis is demonstrated for synthetic arbitrary electromagnetic waves with varying properties typical of observed EMIC waves. The method is also applied to an EMIC wave interval observed by MMS on October 28, 2015. The derived wave properties and k from the wave curl analysis for the observed EMIC wave are compared with the Waves in Homogenous, Anisotropic, Multi-component Plasma (WHAMP) wave dispersion solution and with results from other single- and multi-spacecraft techniques. We find good agreement between k from the wave curl analysis, k determined from other observational techniques, and k determined from WHAMP. Additionally, the variation of k due to the time and frequency intervals used in the wave curl analysis is explored. This exploration demonstrates that the method is robust when applied to a wave containing at least 3–4 wave periods and over a rather wide frequency range encompassing the peak wave emission. These results provide confidence that we are able to directly determine the wave vector properties using this multi-spacecraft method implementation, enabling systematic studies of EMIC wave k properties with MMS

McNair Scholars Research Journal Volume XIII

https://commons.stmarytx.edu/msrj/1012/thumbnail.jp

McNair Scholars Research Journal Volume XIII

https://commons.stmarytx.edu/msrj/1012/thumbnail.jp

Vers la Compression à Tous les Niveaux de la Hiérarchie de la Mémoire

Hardware compression techniques are typically simplifications of software compression methods. They must, however, comply with area, power and latency constraints. This study unveils the challenges of adopting compression in memory design. The goal of this analysis is not to summarize proposals, but to put in evidence the solutions they employ to handle those challenges. An in-depth description of the main characteristics of multiple methods is provided, as well as criteria that can be used as a basis for the assessment of such schemes.Typically, these schemes are not very efficient, and those that do compress well decompress slowly. This work explores their granularity to redefine their perspectives and improve their efficiency, through a concept called Region-Chunk compression. Its goal is to achieve low (good) compression ratio and fast decompression latency. The key observation is that by further sub-dividing the chunks of data being compressed one can reduce data duplication. This concept can be applied to several previously proposed compressors, resulting in a reduction of their average compressed size. In particular, a single-cycle-decompression compressor is boosted to reach a compressibility level competitive to state-of-the-art proposals.Finally, to increase the probability of successfully co-allocating compressed lines, Pairwise Space Sharing (PSS) is proposed. PSS can be applied orthogonally to compaction methods at no extra latency penalty, and with a cost-effective metadata overhead. The proposed system (Region-Chunk+PSS) further enhances the normalized average cache capacity by 2.7% (geometric mean), while featuring short decompression latency.Les techniques de compression matérielle sont généralement des simplifications des méthodes de compression logicielle. Elles doivent, toutefois, se conformer aux contraintes de surface, de puissance et de latence. Cette étude dévoile les défis de l’adoption de la compression dans la conception de la mémoire. Le but de l’analyse n’est pas de résumer les propositions, mais de mettre en évidence les solutions qu’ils emploient pour relever ces défis. Une description détaillée des principales caractéristiques de plusieurs méthodes est fournie, ainsi que des critères qui peuvent être utilisés comme base pour l’évaluation de ces systèmes.Généralement, ces schémas ne sont pas très efficaces, et les schémas qui compressent bien décompressent lentement. Ce travail explore leur granularité pour redéfinir leurs perspectives et améliorer leur efficacité, à travers un concept appelé compression Region-Chunk. Son objectif est d’obtenir un haut (bon) taux de compression et une latence de décompression rapide. L’observation clé est qu’en subdivisant davantage les blocs de données compressés, on peut réduire la duplication des données. Ce concept peut être appliqué à plusieurs compresseurs précédemment proposés, entraînant une réduction de leur taille moyenne compressée. En particulier, un compresseur à décompression à cycle unique est boosté pour atteindre un niveau de compressibilité compétitif par rapport aux propositions de pointe.Enfin, pour augmenter la probabilité de co-allouer avec succès des lignes compressées, Pairwise Space Sharing (PSS) est proposé. PSS peutêtre appliqué orthogonalement aux méthodes de compactage sans pénalité de latence supplémentaire, et avec une surcharge de métadonnées rentable. Le système proposé (Region-Chunk + PSS) améliore encore la capacité normalisé moyenne du cache de 2,7% (moyenne géométrique), tout en offrant une courte latence de décompression

Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)

Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016) Timisoara, Romania. February 8-11, 2016.The PhD Symposium was a very good opportunity for the young researchers to share information and knowledge, to present their current research, and to discuss topics with other students in order to look for synergies and common research topics. The idea was very successful and the assessment made by the PhD Student was very good. It also helped to achieve one of the major goals of the NESUS Action: to establish an open European research network targeting sustainable solutions for ultrascale computing aiming at cross fertilization among HPC, large scale distributed systems, and big data management, training, contributing to glue disparate researchers working across different areas and provide a meeting ground for researchers in these separate areas to exchange ideas, to identify synergies, and to pursue common activities in research topics such as sustainable software solutions (applications and system software stack), data management, energy efficiency, and resilience.European Cooperation in Science and Technology. COS

Prefetching techniques for client server object-oriented database systems

The performance of many object-oriented database applications suffers from the page fetch latency which is determined by the expense of disk access. In this work we suggest several prefetching techniques to avoid, or at least to reduce, page fetch latency. In practice no prediction technique is perfect and no prefetching technique can entirely eliminate delay due to page fetch latency. Therefore we are interested in the trade-off between the level of accuracy required for obtaining good results in terms of elapsed time reduction and the processing overhead needed to achieve this level of accuracy. If prefetching accuracy is high then the total elapsed time of an application can be reduced significantly otherwise if the prefetching accuracy is low, many incorrect pages are prefetched and the extra load on the client, network, server and disks decreases the whole system performance. Access pattern of object-oriented databases are often complex and usually hard to predict accurately. The ..

High prevalence of antibodies to human herpesvirus 8 in relatives of patients with classic Kaposi's sarcoma from Sardinia

A survey for antibodies to a recombinant small viral capsid antigen (sVCA) of human herpesvirus type 8 (HHV‐8) was conducted in Sardinia, one of the world's highest incidence areas for classic Kaposi's sarcoma (KS). Prevalence of antibodies to HHV‐8 sVCA was greatest in patients with KS (95%), followed by family members (39%) and a Sardinian control population age‐ and sex‐matched to the relatives (11%). Within families, prevalence of antibodies was about equal among spouses, children, and siblings of KS patients, a finding that raises the possibilities of intrafamilial person‐to‐person or vertical transmission. Antibodies were detected 2–3 times more frequently in males than in females. The data show that prevalence of antibodies to HHV‐8 sVCA correlates with the distribution of classic KS in a high‐ incidence area. Clustering of seroprevalence within some families suggests the presence of familial risk factors for active HHV‐8 infection

Improving Processor Design by Exploiting Performance Variance

Programs exhibit significant performance variance in their access to microarchitectural structures. There are three types of performance variance. First, semantically equivalent programs running on the same system can yield different performance due to characteristics of microarchitectural structures. Second, program phase behavior varies significantly. Third, different types of operations on microarchitectural structure can lead to different performance. In this dissertation, we explore the performance variance and propose techniques to improve the processor design. We explore performance variance caused by microarchitectural structures and propose program interferometry, a technique that perturbs benchmark executables to yield a wide variety of performance points without changing program semantics or other important execution characteristics such as the number of retired instructions. By observing the behavior of the benchmarks over a range of branch prediction accuracies, we can estimate the impact of a microarchitectural optimization optimization and not the rest of the microarchitecture. We explore performance variance caused by phase changes and develop prediction-driven last-level cache (LLC) writeback techniques. We propose a rank idle time prediction driven LLC writeback technique and a last-write prediction driven LLC writeback technique. These techniques improve performance by reducing the write-induced interference. We explore performance variance caused by different types of operations to Non-Volatile Memory (NVM) and propose LLC management policies to reduce write overhead of NVM.We propose an adaptive placement and migration policy for an STT-RAM-based hybrid cache and writeback aware dynamic cache management for NVM-based main memory system. These techniques reduce write latency and write energy, thus leading to performance improvement and energy reduction