Experimental investigation of adaptive impedance matching for a MIMO terminal with CMOS SOI tuners

It is well known that user proximity introduces absorption and impedance mismatch losses that severely degrade multiple-input multiple-output (MIMO) performance of handset antennas. In this work, we experimentally verified the potential of adaptive impedance matching (AIM) to mitigate user interaction effects and identified the main AIM gain mechanism in realistic systems. A practical setup including custom-designed CMOS silicon-on-insulator (SOI) impedance tuners implemented on a MIMO handset was measured in three propagation environments and 10 real user scenarios. The results indicate that AIM can improve MIMO capacity by up to 42% equivalent to 3.5 dB of multiplexing efficiency (ME) gain. Taking into account the measured losses of 1 dB in the integrated tuners, the maximum net ME gain is 2.5 dB suggesting applicability in practical systems. Variations in ME gains of up to 1.5 dB for different hand-grip styles were mainly due to differences in impedance mismatch and tuner loss distribution. The study also confirmed earlier results on the significant differences in mismatch and absorption between phantoms and real users, in which the phantoms underestimated user effects and therefore AIM gains. Finally, propagation environments of different angular spreads were found to give only minor ME gain variations

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

Development of miniaturized antennas and adaptive tuning solutions for body sensor network applications

Wireless Sensor Networks (WSNs) are currently having a revolutionary impact in rapidly emerging wearable applications such as health and fitness monitoring amongst many others. These types of Body Sensor Network (BSN) applications require highly integrated wireless sensor devices for use in a wearable configuration, to monitor various physiological parameters of the user. These new requirements are currently posing significant design challenges from an antenna perspective. This work addresses several design challenges relating to antenna design for these types of applications. In this thesis, a review of current antenna solutions for WSN applications is first presented, investigating both commercial and academic solutions. Key design challenges are then identified relating to antenna size and performance. A detailed investigation of the effects of the human body on antenna impedance characteristics is then presented. A first-generation antenna tuning system is then developed. This system enables the antenna impedance to be tuned adaptively in the presence of the human body. Three new antenna designs are also presented. A compact, low-cost 433 MHz antenna design is first reported and the effects of the human body on the impedance of the antenna are investigated. A tunable version of this antenna is then developed, using a higher performance, second-generation tuner that is integrated within the antenna element itself, enabling autonomous tuning in the presence of the human body. Finally, a compact sized, dual-band antenna is reported that covers both the 433 MHz and 2.45 GHz bands to provide improved quality of service (QoS) in WSN applications. To date, state-of-the-art WSN devices are relatively simple in design with limited antenna options available, especially for the lower UHF bands. In addition, current devices have no capability to deal with changing antenna environments such as in wearable BSN applications. This thesis presents several contributions that advance the state-of-the-art in this area, relating to the design of miniaturized WSN antennas and the development of antenna tuning solutions for BSN applications

Reconfigurable high efficiency class-F power amplifier using CMOS-MEMS technology

The increasing demand for wireless products to be part of our daily lives brings the need for longer battery lifetime, smaller size and lower cost. To increase battery lifetime, high efficiency power amplifiers (PAs) are needed; To make them smaller, integration or reconfiguration is aimed and to reach lower costs, technologies such as CMOS are final goals. However integration of high efficiency PA in CMOS is challenging due to the technology limitations which restricts the achievable output power and efficiency of the PA. In order to bring solutions for the above-mentioned requirements, in this thesis novel reconfigurable class-F PAs, frequency-reconfiguration, CMOS integration, impedance-reconfiguration and CMOS-MEMS implementation are addressed. Starting with a single frequency operation, a novel class-F PA for mobile applications is proposed in which with a proper harmonic tuning structure the need for extra filtering sections is eliminated, achieving an excellent harmonic-suppression level. This topology uses transmission lines and is developed to cover multiple frequency bands for purpose of global coverage with aim of size reduction. Three novel frequency reconfigurable PAs are proposed using MEMS and semiconductor switches to accomplish class-F operation at two frequencies. The main novelty of this structure is that the reconfiguration is done not only at fundamental frequency but also at harmonics with reduced number of tuning elements. Moreover, by proper placement of the switches in the stubs, the maximum voltages over the switches are minimized. The proposed structure overcomes the narrow band performance of class-F, giving an efficiency more than 60% over a 225 MHz and 175 MHz bandwidth at 900 MHz and 1800 MHz respectively. Measurement results showed high performance at both frequency bands giving 69.5% and 57.9% PAE at 900 MHz and 1800 MHz respectively. A novel CMOS class-F PA is proposed that controls up to the 3rd harmonic and can adapt to load variations due to the effect of the human body on mobile phones. It enables the integration of the PA with other devices in a single chip leading to better matching, higher performance, lower cost and smaller size. In addition, it achieves load impedance reconfigurability by using impedance tuner in its output network and by proper tuning of the network, effects of load variation on the performance are compensated. Two designs at 2.4 GHz have been done using either MOS varactors or MEMS variable capacitors as tuning devices. The design using MOS varactors show a maximum measured values of 26% PAE and 19.2 dBm output power for 50 load. For loads other than 50 ohm an improvement of 15% for PAE and 4.4 dB for output power is obtained in comparison to non-tuned one. The second design is done using MEMS variable capacitors integrated in CMOS technology through a mask-less post-processing technique. Simulations results for 50 ohm load show a peak PAE of 32.8% while delivering 18.2 dBm output power.La creixent demanda de productes sense fils en la nostra vida diària requereix dispositius de menor grandària, menor cost i amb una gran autonomia. Per reduir la mida i augmentar l'autonomia és necessari utilitzar sistemes integrats multiestàndard o reconfigurables, amb amplificadors de RF d'alta eficiència, mentre que per reduir el cost, és preferible utilitzar tecnologies econòmiques com CMOS. No obstant això, la integració en CMOS d'amplificadors de radiofreqüència, i en especial, d'alta eficiència, és un repte a causa de les limitacions de la tecnologia que restringeixen la potència de sortida realitzable i l'eficiència de l'amplificador. En aquesta tesi es tracten els diferents reptes anteriorment esmentats, proposant una nova topologia d'amplificador classe-F amb reconfiguració de freqüència, i proposant la integració d'un amplificador classe-F que s¿adapta a impedància de càrrega variable, implementat en CMOS i CMOS-MEMS. Inicialment en la tesi es proposa una topologia d'amplificador classe-F en què, gràcies a una estructura adequada a la xarxa d'adaptació, s¿elimina la necessitat de filtrat extra, aconseguint un nivell de rebuig d'harmònics excel·lent. La topologia proposada utilitza línies de transmissió i s'ha desenvolupat per dues bandes diferents, amb el disseny orientat a implementar un sistema reconfigurable. S'han aconseguit PAE de l'ordre del 80 % amb potències properes a 10 W. Un cop descrita i analitzada la topologia, s'han proposat tres amplificadors reconfigurables per doble banda freqüencial. Per a la reconfiguració s'han utilitzat MEMS i commutadors basats en semiconductors. L'estructura proposada permet la reconfiguració no només en la freqüència fonamental sinó també en els harmònics, però mantenint un nombre reduït d'elements d'ajust. A més, gràcies a l'adequada col·locació dels commutadors en les línies de transmissió, s'ha minimitzat la tensió màxima en els mateixos. Així mateix, l'estructura proposada evita la característica de banda estreta a classe-F, proporcionant una eficiència superior al 60% en unes amplades de banda de 225 MHz i de 175 MHz, per a les banda de 900 MHz i 1800 MHz respectivament. En aquestes bandes, la PAE màxima mesurada és del 69,5% i del 57,9% respectivament. Finalment, s'ha proposat un amplificador integrat en CMOS, classe-F amb control fins al tercer harmònic. L'amplificador proposat incorpora un sintonitzador a la sortida, podent així adaptar-se a variacions d'impedància de càrrega, típiques en dispositius sense fil (WLAN), degudes a l'efecte del cos humà sobre l'antena. La implementació en CMOS permet la integració de l'amplificador de potència amb altres dispositius en un únic xip, donant lloc a una millor adaptació, millor rendiment, menor cost i menor grandària del sistema. A més, gràcies a l'adaptació a les variacions de la impedància de càrrega, permet mantenir el rendiment en diferents rangs d'operació. S'han realitzat dos dissenys de l'amplificador a 2,4 GHz, un basat en varactors MOS i un altre en condensadors variables MEMS. El disseny que utilitza varactors MOS mostra una PAE màxima del 26% i una potència de 19,2 dBm per a càrrega adaptada 50 ohm. Per altres càrregues, gràcies a l'adaptació d'impedància, s'obté una millora de PAE del 15% i de 4,4 dB en potència de sortida. El disseny utilitzant condensadors MEMS s'integra en CMOS gràcies a post-processat sense màscares addicionals. Els resultats de simulació per a 50 ohm mostren una PAE del 32,8% per 18,2 dBm de potència de sortid

이동통신 기기에 적합한 재구성이 가능한 다중대역 선형 CMOS 전력증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 권영우.In this Dissertation, a study on multiband reconfigurable linear CMOS power amplifier (PA) is performed. Since a larger number of frequency bands is allocated for 3G/4G mobile communication standards nowadays, handset PAs are required to support the ever-increasing number of frequency bands. With the advent of high-speed wireless data transmission, handset PAs are also demanded to perform linear power amplification under the wide-band signal condition. Even though the CMOS technology has cost and size benefits, however, designing a watt-level linear CMOS PA is a challenging issue due to low breakdown voltage and nonlinear nature of the CMOS device. To resolve the issues above, this study presents two methods suitable for multiband (MB) linear CMOS PA: a reconfigurable MB matching structure and a linearization technique. The proposed MB structure shares a PA core to reduce the cost and size, and contains the power- and frequency-reconfigurable matching networks as well as the output path-selection function. Thus, it can perform the MB operation requiring multiple frequency bands and target output powers. The reconfiguration mechanism is quantitatively analyzed and experimentally demonstrated. The fabricated tri-band reconfigurable 3G UMTS PA using an InGaP/GaAs heterojunction bipolar transistor (HBT) process for practical handset application showed minimal efficiency degradation of less than 2% by multi-banding, compared with a single-band reference PA. For linearization of a CMOS PA, a phase-based linearization technique is presented. Since the PA nonlinearity is determined by the dynamic AM-AM and AM-PM, the two distortions should simultaneously be considered in linearization. Contrary to the previous works which have focused on the correction of AM-AM distortion by providing an envelope-dependent gate-bias, this work proposes an AM-PM linearizer using a varactor and an envelope-reshaping circuit. This linearizer helps the PA recover AM-AM distortion as well. To validate the usefulness of the proposed linearizer, 1.88 GHz and 0.9 GHz stacked-FET PAs using a 0.32-μm silicon-on-insulator (SOI) CMOS process were designed and fabricated. Measurement results showed that the fabricated 1.88 / 0.9 GHz linear CMOS PAs achieved linear efficiencies (meeting –39 dBc W-CDMA ACLR) of higher than 44 / 49%. Furthermore, a single-chain MB linear CMOS PA was implemented based on the proposed MB reconfiguration and linearization techniques. The fabricated MB PA, which has two outputs and covers five popular uplink UMTS/LTE bands (Band 1/2/4/5/8: 824 ~ 1980 MHz), showed minimal efficiency degradation (< 3.3%) compared to the single-band dedicated CMOS PA with W-CDMA efficiencies in excess of 40.7%. Finally, the signal-bandwidth limiting effect of the envelope-based linear CMOS PA is discussed and a solution is proposed. Due to the time delay during envelope-detection and shaping, a timing mismatch between the incoming RF signal and envelope-reshaped signal occurs, thus resulting in no linearization effect under wide-band signal (LTE 20 MHz or more) conditions. To resolve the problem, a group delay circuit with a compact size is employed and thus the linearization effect of the proposed phase-based linearizer is maintained up to 40 MHz LTE bandwidth.Abstract i Contents iii List of Tables vi List of Figures vii 1. Introduction 1 1.1 Motivation 1 1.2 Multiband PA Structure 4 1.3 Linearization of CMOS PA 6 1.4 Dissertation Organization 7 1.5 References 9 2. A Multiband Reconfigurable Power Amplifier for 3G UMTS Handset Applications 10 2.1 Introduction 10 2.2 Operation Principle of the Reconfigurable Output Matching Network 12 2.2.1 Power Reconfigurable Network (PRN) 14 2.2.2 Frequency Reconfigurable Network (FRN) 17 2.2.3 Path Selection Network (PSN) 20 2.2.4 Experimental Validation of the PRN and FRN 24 2.3 Fabrication and Measurement of a MB UMTS Reconfigurable PA 26 2.3.1 Design 26 2.3.2 Measurement 31 2.4 Summary 37 2.5 References 38 3. Linearization of CMOS Power Amplifier and Its Multiband Application 41 3.1 Introduction 41 3.2 Linearization of CMOS PAs: Prior Arts 43 3.3 Harmonic Termination 46 3.3.1 Operation Analysis 47 3.3.2 Experimental Validation 52 3.4 Control of Gate Bias Modulation Effect 54 3.4.1 Analysis 54 3.4.2 Experimental Validation 60 3.5 Proposed Linearization #1: Hybrid Bias 67 3.6 Proposed Linearization #2: Phase Injection 71 3.6.1 Motivation 71 3.6.2 Phase (Capacitance) Injection 72 3.7 Linear CMOS PA Design 75 3.7.1 Baseline PA Design 76 3.7.2 Linearizer Design 78 3.7.3 Fabrication 82 3.8 Measurement Results 83 3.8.1 CW Measurement 83 3.8.2 W-CDMA Measurement 84 3.8.3 LTE Measurement 87 3.9 A Single-Chain MB Reconfigurable Linear PA in SOI CMOS 90 3.9.1 MB Linear CMOS PA: Design 90 3.9.2 MB Linear CMOS PA: Measurement 94 3.10 Summary 99 3.11 References 100 4. Linearization of CMOS Power Amplifier Convering Wideband Signal 105 4.1 Introduction 105 4.2 Bandwidth Limitation of Envelope-Based Linearizers 106 4.2.1 Analysis 106 4.2.2 Delay Correction 110 4.2.3 Feedforward Envelope-Detection Structure with a Delay T/L 114 4.3 Group Delay Circuit 117 4.3.1 Positive GDC versus Negative GDC 117 4.3.2 Left-Handed T/L-Based GDC 119 4.4 Fabrication and Measurement 122 4.4.1 GDC Measurement 123 4.4.2 LTE Measurement 124 4.5 Summary 127 4.6 References 128 5. Conclusions 130 5.1 Research Summary 130 5.2 Future Works 132 Abstract in Korean 133 Publications 135Docto