Recursive receiver down-converters with multiband feedback and gain-reuse for low-power applications

Power minimization in wireless transceivers has become increasingly critical in recent years with the emergence of standards for short-distance applications in the 900 MHz and 2.4 GHz industrial, scientific and medical (ISM) radio bands. The demand for long battery life and better portability in such applications has led to extensive research on low power radio architectures. This dissertation introduces receiver topologies for low-power systems and presents a theoretical performance analysis of the topologies. Two fully integrated receiver down-converters that demonstrate the concept are implemented in a 0.13-[mu]m CMOS technology. These topologies employ merged mixers and IF amplifiers in order to reduce power dissipation for a given dynamic range performance. In the described topologies, the input stage of a mixer is used to simultaneously provide conversion gain and baseband amplification. This is achieved by applying the down-converted IF signal to input of the mixer. Consequently, the effective conversion gain of the design is greatly enhanced with current requirement primarily determined by the input transconductor. Potential degradation mechanisms related to instability and second-order distortion are identified and solved by the use of appropriate circuit techniques. Noise and linearity performance of the down-converters is analyzed and compared to that of conventional cascaded design counterparts. The potential for enhancement of IIP3 performance through cancellation of nonlinear products is discussed. Potential extensions of the above work including feedback-based architectures that exploit multiple loops for further maximizing the power efficiency of receiver front-ends are also presented.Electrical and Computer Engineerin

A 0.18-μm BICMOS 20-57 GHz Ultra-Wideband Low-Noise Amplifier Utilizing Frequency-Controlled Positive-Negative Feedback Technique

Silicon based complementary metallic oxide semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) radio frequency integrated circuits (RFICs), including microwave and millimeter-wave (MMW), are attractive for wireless communication and sensing systems due to their small chip size and facilitation in system-on-chip integration. One of the most important RFICs is the low-noise amplifier (LNA). The design of CMOS/BiCMOS wideband LNAs at MMW frequencies, especially those working across several decades of frequency, is challenging due to various issues. For instance, the device parasitic and inter-coupling between nearby elements in highly condensed chip areas limits the operating bandwidth and performance, and the conductive silicon substrates lead to the inevitable low quality factor of passive elements. In this work, a MMW BiCMOS ultra-wideband LNA across 20 to 57 GHz is presented along with the analysis, design and measurement results. To overcome the upper-band gain degradation and improve the in-band flatness, a novel frequency controlled positive-negative (P-N) feedback topology is adopted to modify the gain response by boosting the gain at the upper-band while suppressing that at the lower-band. To reduce overall power consumption, the first and second stages of the amplifier are stacked between supply voltage and DC ground to utilize the same DC current. At the output of amplifier, a shunt-peaking load stage is utilized to achieve wideband output matching. The designed ultra-wideband MMW LNA is fabricated in JAZZ 0.18-μm BiCMOS technology. It shows a measured power gain of 10.5 ± 0.5 dB, a noise figure between 5.1-7.0 dB, input and output return losses better than -10 and -15 dB, respectively, an input 1 dB compression point higher than -19 dBm, and an input third-order intercept point greater than -8 dBm. It dissipates 16.6 mW from 1.8 V DC supply and has a chip area of 700×400 μm^2

A 0.18-μm BICMOS 20-57 GHz Ultra-Wideband Low-Noise Amplifier Utilizing Frequency-Controlled Positive-Negative Feedback Technique

Silicon based complementary metallic oxide semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) radio frequency integrated circuits (RFICs), including microwave and millimeter-wave (MMW), are attractive for wireless communication and sensing systems due to their small chip size and facilitation in system-on-chip integration. One of the most important RFICs is the low-noise amplifier (LNA). The design of CMOS/BiCMOS wideband LNAs at MMW frequencies, especially those working across several decades of frequency, is challenging due to various issues. For instance, the device parasitic and inter-coupling between nearby elements in highly condensed chip areas limits the operating bandwidth and performance, and the conductive silicon substrates lead to the inevitable low quality factor of passive elements. In this work, a MMW BiCMOS ultra-wideband LNA across 20 to 57 GHz is presented along with the analysis, design and measurement results. To overcome the upper-band gain degradation and improve the in-band flatness, a novel frequency controlled positive-negative (P-N) feedback topology is adopted to modify the gain response by boosting the gain at the upper-band while suppressing that at the lower-band. To reduce overall power consumption, the first and second stages of the amplifier are stacked between supply voltage and DC ground to utilize the same DC current. At the output of amplifier, a shunt-peaking load stage is utilized to achieve wideband output matching. The designed ultra-wideband MMW LNA is fabricated in JAZZ 0.18-μm BiCMOS technology. It shows a measured power gain of 10.5 ± 0.5 dB, a noise figure between 5.1-7.0 dB, input and output return losses better than -10 and -15 dB, respectively, an input 1 dB compression point higher than -19 dBm, and an input third-order intercept point greater than -8 dBm. It dissipates 16.6 mW from 1.8 V DC supply and has a chip area of 700×400 μm^2

Design Of Integrated Reconfigurable Rfcmos Low-Noise Amplifiers For Cellular And Wireless Systems

Perkembangan ekstensif dalam dunia komunikasi mudah alih telah menghasilkan cabaran baharu kepada “transceiver” tanpa wayar disebabkan keperluan beroperasi pada pelbagai jalur frekuensi dan piawaian. Perkembangan ini menggalakkan penyelidikan mengenai LNA frekuensi konfigurasi semula berbilang-jalur berbilangpiawaian menggantikan berbilang LNA jalur-tunggal yang selari. Ini dapat mengurangkan keluasan “die” dan lesapan kuasa yang memenuhi keupayaan mudah alih dan kesepaduan yang tinggi. Dalam projek ini, tiga teknik frekuensi konfigurasi semula diperkenalkan bagi mereka bentuk LNA kaskod induktif-ternyahjana dwi-jalur yang berkeupayaan menghasilkan padanan masukan dan hingar serentak walaupun terdapat kekangan kuasa. Semua reka bentuk dilaksanakan menggunakan teknologi 0.13-μm RFCMOS beroperasi pada 900-MHz dan 1900-MHz GSM serta 2450-MHz dan 3650-MHz WLAN. Di samping itu, dua LNA jalur-tunggal telah dibangunkan untuk beroperasi pada 900-MHz dan 2450-MHz bagi tujuan perbandingan. Teknik yang diperkenalkan ialah hibrid teknik kapasitan tersuis, hibrid teknik lebartransistor/ transkonduktans/kapasitan-Miller tersuis dan teknik aruhan boleh ubah berasaskan transformer. Teknik-teknik ini mengurangkan keluasan kapasitor, dan menghasilkan prestasi hingar dan gandaan yang lebih baik bagi kedua-dua jalur di samping mengekalkan pemadanan hingar dan masukan serentak berbanding dengan teknik konfigurasi semula konvensional. Persamaan dihasilkan untuk reka bentuk awal LNA bagi menilai teknik sebelum pelaksanaan. Keputusan simulasi pasca-bentangan dibandingkan dengan keputusan pengukuran bagi penilaian dan pengesahan. Semua reka bentuk LNA dwi-jalur mencapai kelebihan yang dipunyai oleh LNA jalur-tunggal jalur-sempit melalui prestasi mereka yang tinggi di samping mencapai juga kelebihan LNA jalur-lebar disebabkan liputan pelbagai-jalur pelbagai-piawaian. Semua reka bentuk berupaya mencapai angka hingar di antara 1.55 ke 3.97 dB, dengan S11 kurang dari -10 dB, di samping gandaan melebihi 13.4 dB, pada lesapan kuasa di bawah 10 mW bagi semua jalur operasi. Metrik kelelurusan, IIP3 dan P1dB, adalah lebih baik dari masing-masing, -8 dBm dan -21 dBm. Lebar jalur bagi semua LNA adalah cukup untuk meliputi semua jalur piawaian yang dikehendaki. Prestasi ini menunjukkan bahawa semua reka bentuk berupaya untuk memenuhi spesifikasi sasaran bagi jalur 900-MHz, 1900-MHz, 2450-MHz dan 3650-MHz. Sebagai tambahan kepada semua pencapaian ini, satu kaedah baharu berdasarkan analisa elektromagnetik telah dibangunkan yang boleh menggantikan simulasi pasca-bentangan (PLS) menggunakan ekstrak parasitik RC konvensional. Kaedah elektromagnet ini dapat menganggarkan dengan lebih tepat anjakan frekuensi yang dilihat daripada keputusan pengukuran berbanding dengan PLS dengan ekstrak parasitik RC konvensional. Di samping itu, kaedah ini juga boleh membantu pereka bentuk untuk diagnos dengan lebih tepat reka bentuk LNA bersepadu-penuh tanpa komponen luar-cip sebelum rekabentuk itu difabrikasi. ________________________________________________________________________________________________________________________ The extensive growth in worldwide mobile communications has introduced new challenges to wireless transceivers as they need to operate at a variety of frequency bands and standards. This encourages researches on multi-band multi-standard frequency-reconfigurable LNAs as an option to multiple parallel single-band LNAs. This reduces the die area and power consumption and provides higher mobility and integration. In this work, three frequency-reconfigurable techniques were introduced to design dual-band inductively-degenerated cascode LNAs with power-constrained simultaneous noise and input matching capability. The designs were implemented in 0.13-μm RFCMOS technology to operate at 900-MHz and, 1900-MHz GSM, and 2450-MHz and 3650-MHz WLAN standard bands. In addition to dual-band LNAs, two single band LNAs were developed to operate at 900-MHz and 2450-MHz for comparison purpose. The techniques introduced were hybrid of switched capacitances technique, hybrid of switched transistor-width/transconductance/Miller-capacitance technique and transformer-based variable inductance technique. The techniques introduced less capacitor area, better noise and gain performances for both bands and preserved simultaneous noise and input matching compared to conventional reconfigurable techniques. Equations were developed for initial LNA designs to evaluate the techniques before implementation. The post-layout simulation results were compared to measurement results for evaluation and verification. The measured results satisfied all objectives of this work. The dual-band LNA designs showed advantages of a single-band narrow-band LNA because of its high performance together with the advantage of a wideband LNA because of its multi-band multistandard coverage. For all operating bands, all designs could achieve noise figure between 1.55 and 3.97 dB with S11 less than -10 dB as well as gains more than 13.4 dB while the power consumption were lower than 10 mW. IIP3 and P1dB as linearity metrics were better than -8 dBm and -21 dBm, respectively. The bandwidth for all LNAs were sufficient to cover the required bands for desired standards. These performances show that all design are able to meet the targeted specification for 900- MHz, 1900-MHz, 2450-MHz and 3650-MHz bands. In addition to these findings, a new method based on electromagnetic analysis was developed that can replace the conventional post-layout simulation with RC parasitic extraction. The electromagnetic method predicted the frequency shift observed in the measurement more accurately than the conventional PLS with RC parasitic extraction. Also, using this method, designers are able to diagnose the fully-integrated LNA designs with no off-chip component before fabrication more precisely

Design Solutions For Modular Satellite Architectures

The cost-effective access to space envisaged by ESA would open a wide range of new opportunities and markets, but is still many years ahead. There is still a lack of devices, circuits, systems which make possible to develop satellites, ground stations and related services at costs compatible with the budget of academic institutions and small and medium enterprises (SMEs). As soon as the development time and cost of small satellites will fall below a certain threshold (e.g. 100,000 to 500,000 €), appropriate business models will likely develop to ensure a cost-effective and pervasive access to space, and related infrastructures and services. These considerations spurred the activity described in this paper, which is aimed at: - proving the feasibility of low-cost satellites using COTS (Commercial Off The Shelf) devices. This is a new trend in the space industry, which is not yet fully exploited due to the belief that COTS devices are not reliable enough for this kind of applications; - developing a flight model of a flexible and reliable nano-satellite with less than 25,000€; - training students in the field of avionics space systems: the design here described is developed by a team including undergraduate students working towards their graduation work. The educational aspects include the development of specific new university courses; - developing expertise in the field of low-cost avionic systems, both internally (university staff) and externally (graduated students will bring their expertise in their future work activity); - gather and cluster expertise and resources available inside the university around a common high-tech project; - creating a working group composed of both University and SMEs devoted to the application of commercially available technology to space environment. The first step in this direction was the development of a small low cost nano-satellite, started in the year 2004: the name of this project was PiCPoT (Piccolo Cubo del Politecnico di Torino, Small Cube of Politecnico di Torino). The project was carried out by some departments of the Politecnico, in particular Electronics and Aerospace. The main goal of the project was to evaluate the feasibility of using COTS components in a space project in order to greatly reduce costs; the design exploited internal subsystems modularity to allow reuse and further cost reduction for future missions. Starting from the PiCPoT experience, in 2006 we began a new project called ARaMiS (Speretta et al., 2007) which is the Italian acronym for Modular Architecture for Satellites. This work describes how the architecture of the ARaMiS satellite has been obtained from the lesson learned from our former experience. Moreover we describe satellite operations, giving some details of the major subsystems. This work is composed of two parts. The first one describes the design methodology, solutions and techniques that we used to develop the PiCPoT satellite; it gives an overview of its operations, with some details of the major subsystems. Details on the specifications can also be found in (Del Corso et al., 2007; Passerone et al, 2008). The second part, indeed exploits the experience achieved during the PiCPoT development and describes a proposal for a low-cost modular architecture for satellite

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Dual-band FSK receiver and building block design for UWB impulse radio

Master'sMASTER OF ENGINEERIN

Switchable wideband receiver frontend for 5G and satellite applications

Modern day communication architectures provides the requirement for interconnected devices offering very high data rate (more than 10 Gbps), low latency, and support for multiple service integration across existing communication generations with wideband spectrum coverage. An integrated satellite and 5G architecture switchable receiver frontend is presented in this thesis, consisting of a single pole double throw (SPDT) switch and two low noise amplifiers (LNAs) spanning X-band and K/Ka-band frequencies. The independent X-band LNA (8-12 GHz) has a gain of 38 dB at a centre design frequency of 9.8 GHz, while the K/Ka-band (23-28 GHz) has a gain of 29 GHz at a centre design frequency of 25.4 GHz. Both LNAs are a three-stage cascaded design with separated gate and drain lines for each transistor stage. The broadband high isolation single pole double throw (SPDT) switch based on a 0.15 μm gate length Indium Gallium Arsenide (InGaAs) pseudomorphic high electron transistor (pHEMT) is designed to operate at the frequency range of DC-50 GHz with less than 3 dB insertion loss and more than 40 dB isolation. The switch is designed to improve the overall stability of the system and the gain. A gain of about 25 dB is achieved at 9.8 GHz when the X-band arm is turned on and the K/Ka-band is turned off. A gain of about 23 dB is achieved at 25.4 GHz when the K/Ka-band arm is turned on and the X-band arm is off. This presented switchable receiver frontend is suitable for radar applications, 5G mobile applications, and future broadband receivers in the millimetre wave frequency range