Design Techniques of Energy Efficient PLL for Enhanced Noise and Lock Performance

Phase locked loops(PLLs)are vital building blocks of communication sys-tems whose performance dictates the quality of communication.The design of PLL to o_er superior performance is the prime objective of this research.It is desirable for the PLL to have fast locking,low noise,low reference spur,wide lock range,low power consumption consuming less silicon area.To achieve these performance parameters simultaneously in a PLL being a challenging task is taken up as a scope of the present work.A comprehensive study of the performance linked PLL components along with their design challenges is made in this report.The phase noise which is directly related to the dead zone of the PLL is minimized using an e_cient phase frequency detector(PFD)in this thesis.Here a voltage variable delay element is inserted in the reset path of the PFD to reduce the dead zone.An adaptive PFD architecture is also proposed to have a low noise and fast PLL simultaneously.In this work,before locking a fast PFD and in the locked state a low noise PFD operates to dictate the phase di_erence of the reference and feedback signals.To reduce the reference spur,a novel charge pump architecture is proposed which eventually reduces the lock time up to a great extent.In this charge pump a single current source is employed to reduce the output current mis-match and transmission gates are used to reduce the non ideal e_ects.Besides this,the fabrication process variations have a predominant e_ect on the PLL performance,which is directly linked to the locking capability.This necessitates a manufacturing process variation tolerant design of the PLL.In this work an e_cient multi-objective optimization method is also applied to at-tain multiple optimal performance objectives.The major performances under consideration are lock time,phase noise,lock range and power consumption

Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

Nonlinear Circuits For Signal Generation And Processing In Cmos

As Moore's law predicted, transistor scaling has continued unabated for more than half a century, resulting in significant improvement in speed, efficiency, and integration level. This has led to rapid growth of diverse computing and communications technologies, including the Internet and mobile telephony. Nevertheless, we still face the fundamental limit of noise from transistors and passive components. This noise limit becomes more critical at higher frequencies due to the decrease in intrinsic transistor gain as well as with voltage scaling that accompanies the transistor scaling. On the other hand, insufficient transistor gain and breakdown in silicon limits high-power signal generation at sub-millimeter frequencies that is essential in many security and medical applications, including detection of concealed weapons and bio/molecular spectroscopy for drug detection and breath analysis for disease diagnosis. To go beyond these limits, we propose a new circuit design methodology inspired by nonlinear wave propagation. This method is closely related to intriguing phenomena in other disciplines of physics such as nonlinear optics, fluid mechanics, and plasma physics. Based on this, in the first part of this study, we propose a passive 20-GHz frequency divider for the first time implemented in CMOS. This device has close to ideal noise performance with no DC power consumption, which can potentially reduce overall system power and phase noise in high-frequency synthesizers. Next, to achieve sensitivity toward the thermal noise limit, we propose a 10-GHz CMOS noise-squeezing amplifier. This amplifier enhances sensitivity of an input signal in one quadrature phase by 2.5 dB at the expense of degrading the other quadrature component. Lastly, we introduce an LC lattice to generate 2.7 V p[-] p , 6 ps pulses in CMOS using constructive nonlinear wave interaction. The proposed lattice exhibits the sharpest pulse width achieved for high-amplitude pulses (>1 V) in any CMOS processes

Design of CMOS integrated phase-locked loops for multi-gigabits serial data links

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 üm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 üm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 üm CMOS technology

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

The availability of quantum microprocessors is mandatory, to efficiently run those quantum al-gorithms promising a radical leap forward in computation capability. Silicon-based nanostruc-tured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthe-size control signals for spintronic qubits. In a quantum microprocessor, these circuits should op-erate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been sys-tematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physi-cal models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guide-lines for the VCO/FD interface, useful in the absence of cryogenic DKs

Synthèses de fréquence à bas bruit basées sur des oscillateurs opto-électroniques couplés intégrées en technologie BiCMOS SiGe 130nm

Les hyperfréquences jouent un rôle indispensable dans le domaine des télécommunications, que ce soit pour la téléphonie mobile, les radars automobiles, le Wi-Fi ou encore la transmission satellitaire, sans que cette liste ne soit évidemment exhaustive. Pour l'ensemble de ces applications omniprésentes dans la société actuelle, ce sont ces signaux hyperfréquences qui servent de porteuses pour transmettre l'information sur de plus ou moins longues distances. Les méthodes de génération de signaux hyperfréquences actuelles sont basées sur des boucles à verrouillage de phase (PLL). Elles réalisent une multiplication d'une fréquence de référence basse de quelques dizaines à quelques centaines de mégahertz pour l'amener à quelques gigahertz voire dizaines de gigahertz. Il y a cependant un inconvénient majeur lié à cette méthode : synthétiser une fréquence par multiplication d'une référence basse s'accompagne d'une augmentation théorique du bruit de phase du signal généré, d'autant plus que le rapport de multiplication est élevé. À l'inverse, une synthèse par division de fréquence diminue le bruit de phase théorique. Or on voit apparaître depuis quelques années des références à des fréquences déjà élevées, basées sur des oscillateurs optoélectroniques couplés (COEO), qui peuvent dès lors servir à réaliser des synthèses basées sur de la division de fréquence, et c'est dans ce cadre que se situe le travail de cette thèse. Nous utilisons pour référence de fréquence, des COEO qui génèrent un signal de fréquence élevée à haute pureté spectrale, à 10 et 30 GHz. L'objectif est alors d'être capable de générer des signaux dont la fréquence est inférieure à 30 GHz et aussi basse que 1 GHz. Ces signaux synthétisés doivent conserver autant que possible la pureté spectrale du signal de référence en pénalisant le moins possible le bénéfice théorique apporté par la division. Cette thèse décrit la conception de diviseurs hyperfréquences à très faible bruit de phase résiduel disposant au final de rapports de division fractionnaires et/ou programmables. Dans un premier temps, nous avons conçu des diviseurs de rapports fixes afin d'estimer les performances en bruit de phase atteignables à cette fréquence de travail sur les technologies utilisées. Plusieurs diviseurs ECL par 2 et par 3 ont été conçus, fabriqués et mesurés pour une division jusqu'à 30 GHz. Un diviseur CMOS par 10 ainsi qu'une technique de resynchronisation permettant d'annuler la majeure partie du bruit de phase de la chaîne de division sont également présentés. Plusieurs diviseurs analogiques à rang fixe ont également été conçus, bien que s'étant révélés moins performants au final : un diviseur à verrouillage par injection (ILFD) et un diviseur à renforcement du second harmonique, qui réalisent tous les deux une division par 3 autour de 30 GHz. Pour terminer, nous avons conçu des diviseurs fractionnaires large bande fonctionnant au moins jusqu'à 30 GHz et offrant des performances en bruit de phase compétitives. Si ces modèles s'inspirent du principe régénératif connu de Miller, nous en proposons une déclinaison tout à fait originale. Une première série de diviseurs fractionnaires fixes a ainsi été réalisée pour des rapports fixes de 1,25, 2,5 et 4,5. Pour terminer, un diviseur fractionnaire dont la partie décimale est programmable a été ensuite été réalisé et mesuré. Il s'agit d'un diviseur fractionnaire dont la partie entière du rapport de division est 4 et la partie décimale codée sur 4 bits.Microwave signals are essential in the field of telecommunications whether for mobile telephony, automotive radar, Wi-Fi or even satellite transmission, without this list being exhaustive. For all these ubiquitous applications in our current society, microwave signals are the carriers for the transmission of information from a system to another. Microwave signals synthesis techniques are mostly based on Phase-Locked Loop (PLL). PLL multiply a low frequency reference ranging from a dozen to a few hundred megahertz toward a few gigahertz to a few dozen gigahertz. However, there is one main drawback with this synthesis technique: synthesizing a frequency by multiplying a low frequency reference induces an unavoidable rise of the theoretical phase noise of the synthesized signal, even more if the multiplication factor is high. On the contrary, frequency synthesis by division lowers the theoretical phase noise. Yet, high frequency high spectral purity frequency references called Coupled OptoElectronic Oscillator (COEO) are being developed for a few years. They are perfect candidate to be used as reference for frequency synthesis by division, and this is within this framework that our research takes place. We use as frequency references two COEO generating high spectral purity signals at 10 and 30?GHz. The aim of our work is then to be able to generate different signals whose frequencies are below 30?GHz and as low as 1?GHz. These synthesized signals must preserve as much as possible the spectral purity of the reference while deteriorating as less as possible the theoretical benefit brought by the division. This thesis describes the conception of low residual phase noise microwave frequency dividers operating, for the most evolved ones, fractional and/or programmable division ratios. In a first place, we designed static frequency dividers in order to estimate the phase noise performance that we can conceivably reach with the technology we use. Several ECL dividers by 2 and by 3 are designed, fabricated and measured for a division up to 30?GHz. A CMOS divider by 10 along with a resynchronization technique allowing to cancel most of the phase noise in a cascaded divider are also presented. In a second place, we designed analog dividers, although they have proven to be less competitive than digital dividers: an Injection-Locked Frequency Divider (ILFD) and a regenerative second-harmonic frequency divider, both realising a frequency division by 3 around 30 GHz. Finally, we designed wideband fractional dividers operating at least at 30 GHz with competitive phase noise performance. Even though they are inspired by Miller's regenerative frequency dividers, we introduce here an innovative declination of fractional dividers. A first series of static fractional dividers has been designed with ratios of 1.25, 2.5 and 4.5. Ultimately, a fractional divider with a programmable decimal part has been designed and measured. This divider has an integer part of 4 and a decimal part programmed on 4 bits

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

Imepdance Sensing Techniques for Integrated Circuits Sensor Applications

Impedance measurements are increasingly demanded in modern CMOS sensing systems as impedance is the most common electrical signal obtained from sensors, delivering physical, chemical and biomedical quantity changes. Impedance sensing for wide interested frequency, broad dynamic range, and various sensor interfaces has numerous challenges, especially targeted in CMOS miniaturization with power and area limitation. In this thesis, first, a low power impedance-based cytometer architecture for cell analysis applications is presented. Fabricated in 0.18μm CMOS process with 6pArms input-referred noise over 200Hz bandwidth at 0.5 MHz modulation frequency, the impedance sensor demonstrates in detecting 3μm diameter particles. Secondly, using impedance sensing technique, a low-power RC oscillator based on IQ-balanced impedance sensing FLL is designed and demonstrated, achieving 25.4ppm/°C across temperature variation and 0.27%/V across supply variation at 650kHz output frequency