The Use of MPI and OpenMP Technologies for Subsequence Similarity Search in Very Large Time Series on Computer Cluster System with Nodes Based on the Intel Xeon Phi Knights Landing Many-core Processor

Nowadays, subsequence similarity search is required in a wide range of time series mining applications: climate modeling, financial forecasts, medical research, etc. In most of these applications, the Dynamic TimeWarping (DTW) similarity measure is used since DTW is empirically confirmed as one of the best similarity measure for most subject domains. Since the DTW measure has a quadratic computational complexity w.r.t. the length of query subsequence, a number of parallel algorithms for various many-core architectures have been developed, namely FPGA, GPU, and Intel MIC. In this article, we propose a new parallel algorithm for subsequence similarity search in very large time series on computer cluster systems with nodes based on Intel Xeon Phi Knights Landing (KNL) many-core processors. Computations are parallelized on two levels as follows: through MPI at the level of all cluster nodes, and through OpenMP within one cluster node. The algorithm involves additional data structures and redundant computations, which make it possible to effectively use the capabilities of vector computations on Phi KNL. Experimental evaluation of the algorithm on real-world and synthetic datasets shows that it is highly scalable.Comment: Accepted for publication in the "Numerical Methods and Programming" journal (http://num-meth.srcc.msu.ru/english/, in Russian "Vychislitelnye Metody i Programmirovanie"), in Russia

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

The number of functionalities controlled by software on every critical real-time product is on the rise in domains like automotive, avionics and space. To implement these advanced functionalities, software applications increasingly adopt artificial intelligence algorithms that manage massive amounts of data transmitted from various sensors. This translates into unprecedented memory performance requirements in critical systems that the commonly used DRAM memories struggle to provide. High-Bandwidth Memory (HBM) can satisfy these requirements offering high bandwidth, low power and high-integration capacity features. However, it remains unclear whether the predictability and isolation properties of HBM are compatible with the requirements of critical embedded systems. In this work, we perform to our knowledge the first timing analysis of HBM. We show the unique structural and timing characteristics of HBM with respect to DRAM memories and how they can be exploited for better time predictability, with emphasis on increased isolation among tasks and reduced worst-case memory latency.This work has been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB-C21/AEI/10.13039/501100011033; the European Union’s Horizon 2020 Framework Programme under grant agreement No. 878752 (MASTECS) and agreement No. 779877 (Mont-Blanc 2020); the European Research Council (ERC) grant agreement No. 772773 (SuPerCom); and the Natural Sciences and Engineering Research Council of Canada (NSERC)Peer ReviewedPostprint (author's final draft

Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives

© ACM, 2020. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in ACM Computing Surveys, Vol. 53, No. 5, Article 95. Publication date: September 2020. https://doi.org/10.1145/3403956[EN] Performance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due to the exponential increase in the number of devices per chip, to higher system fault rates. Consequently, High-performance Computing (HPC) systems need to integrate prediction, detection, and recovery mechanisms to cope with faults efficiently. This article reviews fault detection, fault prediction, and recovery techniques in HPC systems, from electronics to system level. We analyze their strengths and limitations. Finally, we identify the promising paths to meet the reliability levels of Exascale systems.This work has received funding from the European Union's Horizon 2020 (H2020) research and innovation program under the FET-HPC Grant Agreement No. 801137 (RECIPE). Jaume Abella was also partially supported by the Ministry of Economy and Competitiveness of Spain under Contract No. TIN2015-65316-P and under Ramon y Cajal Postdoctoral Fellowship No. RYC-2013-14717, as well as by the HiPEAC Network of Excellence. Ramon Canal is partially supported by the Generalitat de Catalunya under Contract No. 2017SGR0962.Canal, R.; Hernández Luz, C.; Tornero-Gavilá, R.; Cilardo, A.; Massari, G.; Reghenzani, F.; Fornaciari, W.... (2020). Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives. ACM Computing Surveys. 53(5):1-32. https://doi.org/10.1145/3403956S132535Abella, J., Hernandez, C., Quinones, E., Cazorla, F. J., Conmy, P. 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IEEE Internet Com

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430 MHz, our fault-tolerant cluster achieves up to 1160 MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm2, representing a 1.3% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm2, namely ~9.4% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the redundant modes with minimum performance loss, allowing execution of a mission-critical or a performance section, with <400 clock cycles overhead for entry and exit. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs

Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code

High-level synthesis (HLS) is an increasingly popular method for generating hardware from a description written in a software language like C/C++. Traditionally, HLS tools have operated on sequential code, however, in recent years there has been a drive to synthesise multi-threaded code. In this context, a major challenge facing HLS tools is how to automatically partition memory among parallel threads to fully exploit the bandwidth available on an FPGA device and minimise memory contention. Existingpartitioning approaches require inefficient arbitration circuitry to serialise accesses to each bank because they make conservative assumptions about which threads might access which memory banks. In this article, we design a static analysis that can prove certain memory banks are only accessed by certain threads, and use this analysis to simplify or even remove the arbiters while preserving correctness. We show how this analysis can be implemented using the Microsoft Boogie verifier on top of satisfiability modulo theories (SMT) solver, and propose a tool named EASY using automatic formal verification. Our work supports arbitrary input code with any irregular memory access patterns and indirect array addressing forms. We implement our approach in LLVM and integrate it into the LegUp HLS tool. For a set of typical application benchmarks our results have shown that EASY can achieve 0.13×(avg. 0.43×) of area and 1.64×(avg. 1.28×) of performance compared to the baseline, with little additional compilation time relative to the long time in hardware synthesis

Revisiting the high-performance reconfigurable computing for future datacenters

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects-discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well

Beef Flavor Audit

Consumer acceptability in meat flavor is one of the driving factors of consumer acceptability. Many factors have been found that affect beef flavor, but little is known about variability of major beef cuts in the retail meat case. In this study four beef cuts (chuck roast = 50, top sirloin steaks = 49, top loin steaks =50, and 80% lean ground beef = 50) were obtained from various retail stores in Miami, Los Angeles, Portland, New York, and Denver during a two-month period. No specific requirements such as quality grade, grain fed, or grass fed were used when purchasing cuts except ground beef was standardize to a 20 % fat level. A wide variety of samples that were from different production systems or contained claims that would be available to a customer during a shopping trip were documented. Two types of cooking methods were utilized; food service grill for top loin, top sirloin, and ground beef and oven roasting for chuck roast. Beef was cooked to an internal temperature of 71˚C. An expert, trained descriptive flavor and texture sensory panel evaluated beef flavor, aroma and texture attributes. Principal component and partial least square biplots were conducted to relate flavor attributes and aromatic volatile compounds. Ground beef was more intense (P < 0.0001) levels of beef flavor identity, brown, and roasted flavor aromatic and salt and umami basic tastes. Chuck roasts were closely associated with volatile compounds such as hexanal, 1- pentanol, 1-octen-3-ol, and 2-octenal, lipid degradation products. Top sirloin steaks were lowest (P< 0.0001) in fat- like flavor aromatics, and more intense (P< 0.0001) in burnt and cardboardy flavor aromatics and bitter and sour basic tastes. Top sirloin steaks and chuck roasts were more intense in metallic and liver-like (P< 0.0001) flavor aromatics. Top sirloin steaks were clustered near thiobis methane, ethyl ester acetic acid, and methyl ester butanoic acid. Top loin steaks were intermediate in flavor attributes, but possessed volatile products found from the Maillard reaction. Chuck roasts were closely associated with bloody/serumy flavor aromatics. Ground beef patties were clustered with fat-like, overall sweet, green hay, and buttery flavor aromatics. Top sirloin steaks were more highly associated with off-flavors, such as liver-like, cardboardy, and sour flavor aromatics. Top loin steaks were clustered with more positive attributes such as umami, beef flavor identity, brown, and roasted flavor aromatics. Therefore, flavor descriptive attributes of four beef cuts differed. Chuck roasts and top sirloin steaks were more closely associated with negative flavor attributes. Ground beef tended to contain more of the sweet, fatlike flavor attributes. Volatiles clustered around ground beef helped to explain the presence of green hay like flavor. Top loin steaks were associated with more positive beef flavor attributes

Beef Flavor Audit

Consumer acceptability in meat flavor is one of the driving factors of consumer acceptability. Many factors have been found that affect beef flavor, but little is known about variability of major beef cuts in the retail meat case. In this study four beef cuts (chuck roast = 50, top sirloin steaks = 49, top loin steaks =50, and 80% lean ground beef = 50) were obtained from various retail stores in Miami, Los Angeles, Portland, New York, and Denver during a two-month period. No specific requirements such as quality grade, grain fed, or grass fed were used when purchasing cuts except ground beef was standardize to a 20 % fat level. A wide variety of samples that were from different production systems or contained claims that would be available to a customer during a shopping trip were documented. Two types of cooking methods were utilized; food service grill for top loin, top sirloin, and ground beef and oven roasting for chuck roast. Beef was cooked to an internal temperature of 71˚C. An expert, trained descriptive flavor and texture sensory panel evaluated beef flavor, aroma and texture attributes. Principal component and partial least square biplots were conducted to relate flavor attributes and aromatic volatile compounds. Ground beef was more intense (P < 0.0001) levels of beef flavor identity, brown, and roasted flavor aromatic and salt and umami basic tastes. Chuck roasts were closely associated with volatile compounds such as hexanal, 1- pentanol, 1-octen-3-ol, and 2-octenal, lipid degradation products. Top sirloin steaks were lowest (P< 0.0001) in fat- like flavor aromatics, and more intense (P< 0.0001) in burnt and cardboardy flavor aromatics and bitter and sour basic tastes. Top sirloin steaks and chuck roasts were more intense in metallic and liver-like (P< 0.0001) flavor aromatics. Top sirloin steaks were clustered near thiobis methane, ethyl ester acetic acid, and methyl ester butanoic acid. Top loin steaks were intermediate in flavor attributes, but possessed volatile products found from the Maillard reaction. Chuck roasts were closely associated with bloody/serumy flavor aromatics. Ground beef patties were clustered with fat-like, overall sweet, green hay, and buttery flavor aromatics. Top sirloin steaks were more highly associated with off-flavors, such as liver-like, cardboardy, and sour flavor aromatics. Top loin steaks were clustered with more positive attributes such as umami, beef flavor identity, brown, and roasted flavor aromatics. Therefore, flavor descriptive attributes of four beef cuts differed. Chuck roasts and top sirloin steaks were more closely associated with negative flavor attributes. Ground beef tended to contain more of the sweet, fatlike flavor attributes. Volatiles clustered around ground beef helped to explain the presence of green hay like flavor. Top loin steaks were associated with more positive beef flavor attributes