Encryption AXI Transaction Core for Enhanced FPGA Security

The current hot topic in cyber-security is not constrained to software layers. As attacks on electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz.This work has been supported within the fund for research groups of the Basque university system IT1440-22 by the Department of Education and within the PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects by the Hazitek program, both of the Basque Government, the latter also by the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and IDI-20220543 and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds)

Enabling Intelligent IoTs for Histopathology Image Analysis Using Convolutional Neural Networks

Medical imaging is an essential data source that has been leveraged worldwide in healthcare systems. In pathology, histopathology images are used for cancer diagnosis, whereas these images are very complex and their analyses by pathologists require large amounts of time and effort. On the other hand, although convolutional neural networks (CNNs) have produced near-human results in image processing tasks, their processing time is becoming longer and they need higher computational power. In this paper, we implement a quantized ResNet model on two histopathology image datasets to optimize the inference power consumption. We analyze classification accuracy, energy estimation, and hardware utilization metrics to evaluate our method. First, the original RGBcolored images are utilized for the training phase, and then compression methods such as channel reduction and sparsity are applied. Our results show an accuracy increase of 6% from RGB on 32-bit (baseline) to the optimized representation of sparsity on RGB with a lower bit-width, i.e., \u3c8:8\u3e. For energy estimation on the used CNN model, we found that the energy used in RGB color mode with 32-bit is considerably higher than the other lower bit-width and compressed color modes. Moreover, we show that lower bit-width implementations yield higher resource utilization and a lower memory bottleneck ratio. This work is suitable for inference on energy-limited devices, which are increasingly being used in the Internet of Things (IoT) systems that facilitate healthcare systems

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

In this article, authors explore radiation hardening techniques through the design of a test chip implemented in 16-nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multiplication were taped out and irradiated with neutrons. The results obtained from the neutron campaign revealed that the radiation-hardened variants present superior resiliency when either local or global triple modular redundancy (TMR) schemes are employed. Furthermore, simulation-based fault injection was utilized to validate the measurements and to explore the effects of different implementation strategies on failure rates. We further show that the interplay between these different implementation strategies is not trivial to capture and that synthesis optimizations can effectively break assumptions about the effectiveness of redundancy schemes

Digital in-memory stochastic computing architecture for vector-matrix multiplication

The applications of the Artificial Intelligence are currently dominating the technology landscape. Meanwhile, the conventional Von Neumann architectures are struggling with the data-movement bottleneck to meet the ever-increasing performance demands of these data-centric applications. Moreover, The vector-matrix multiplication cost, in the binary domain, is a major computational bottleneck for these applications. This paper introduces a novel digital in-memory stochastic computing architecture that leverages the simplicity of the stochastic computing for in-memory vector-matrix multiplication. The proposed architecture incorporates several new approaches including a new stochastic number generator with ideal binary-to-stochastic mapping, a best seeding approach for accurate-enough low stochastic bit-precisions, a hybrid stochastic-binary accumulation approach for vector-matrix multiplication, and the conversion of conventional memory read operations into on-the-fly stochastic multiplication operations with negligible overhead. Thanks to the combination of these approaches, the accuracy analysis of the vector-matrix multiplication benchmark shows that scaling down the stochastic bit-precision from 16-bit to 4-bit achieves nearly the same average error (less than 3%). The derived analytical model of the proposed in-memory stochastic computing architecture demonstrates that the 4-bit stochastic architecture achieves the highest throughput per sub-array (122 Ops/Cycle), which is better than the 16-bit stochastic precision by 4.36x, while still maintaining a small average error of 2.25%

RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures

Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as the "memory wall" and severely limits the performance of a microprocessor. One of the most promising solutions is the "logic-in-memory" approach. It consists of merging memory and logic units, enabling data to be processed directly inside the memory itself. Here we propose an RISC-V framework that supports logic-in-memory operations. We substitute data memory with a circuit capable of storing data and of performing in-memory computation. The framework is based on a standard memory interface, so different logic-in-memory architectures can be inserted inside the microprocessor, based both on CMOS and emerging technologies. The main advantage of this framework is the possibility of comparing the performance of different logic-in-memory solutions on code execution. We demonstrate the effectiveness of the framework using a CMOS volatile memory and a memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in algorithm execution speed and a reduction in energy consumption

A security model for randomization-based protected caches

Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention. This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question. In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache sidechannel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.This research was supported by the European Union Regional Development Fund withinthe framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of50% of the total cost eligible, under the DRAC project [001-P-001723], and by the SpanishGovernment, under the CONSENT project [RTI2018-095094-B-C21]. Carles Hernándezis partially supported by Spanish Ministry of Science, Innovation and Universities under“Ramón y Cajal”, fellowship No. RYC2020-030685-I. Vatistas Kostalabros is partiallysupported by the Agency for Management of University and Research Grants (AGAUR) ofthe Government of Catalonia, under “Ajuts per a la contractació de personal investigadornovell”, fellowship No. 2019FI B01274. Miquel Moretó is partially supported by theSpanish Ministry of Economy, Industry and Competitiveness under “Ramón y Cajal”,fellowship No. RYC-2016-21104.Peer ReviewedPostprint (published version

A security model for randomization-based protected caches

Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention. This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question. In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache sidechannel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.This research was supported by the European Union Regional Development Fund withinthe framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of50% of the total cost eligible, under the DRAC project [001-P-001723], and by the SpanishGovernment, under the CONSENT project [RTI2018-095094-B-C21]. Carles Hernándezis partially supported by Spanish Ministry of Science, Innovation and Universities under“Ramón y Cajal”, fellowship No. RYC2020-030685-I. Vatistas Kostalabros is partiallysupported by the Agency for Management of University and Research Grants (AGAUR) ofthe Government of Catalonia, under “Ajuts per a la contractació de personal investigadornovell”, fellowship No. 2019FI B01274. Miquel Moretó is partially supported by theSpanish Ministry of Economy, Industry and Competitiveness under “Ramón y Cajal”,fellowship No. RYC-2016-21104.Peer ReviewedPostprint (published version

A comparison between two optimisation alternatives for mapping in wireless network on chip

Network on Chip (NoC) is a well known approach that aims at improving the performance of many-core systems. The design of such systems involves the optimal mapping of tasks to nodes, and the corresponding scheduling of the tasks at every node, which results in a challenging optimisation problem considering the constraints that need to be respected. In this paper, after formalising the problem and elaborating on its complexity, we present an AI approach to solve the problem and evaluate it against a MIP approach. Our empirical evaluation shows that the AI approach is able to obtain solutions of good quality very quickly

Calibration of ring oscillator-based integrated temperature sensors for power management systems

ABSTRACT: This paper details the development and validation of a temperature sensing methodology using an un-trimmed oscillator-based integrated sensor implemented in the 0.18-μm SOI XFAB process, with a focus on thermal monitoring in system-on-chip (SoC) based DC-DC converters. Our study identifies a quadratic relationship between the oscillator output frequency and temperature, which forms the basis of our proposed calibration mechanism. This mechanism aims at mitigating process variation effects, enabling accurate temperature-to-frequency mapping. Our research proposes and characterizes several trimming-free calibration techniques, covering a spectrum from zero to thirty-one frequency-temperature measurement points. Notably, the Corrected One-Point calibration method, requiring only a single ambient temperature measurement, emerges as a practical solution that removes the need for a temperature chamber. This method, after adjustment, successfully reduces the maximum error to within ±2.95 °C. Additionally, the Two-Point calibration method demonstrates improved precision with a maximum positive error of +1.56 °C at −15 °C and a maximum negative error of −3.13 °C at +10 °C (R2 value of 0.9958). The Three-Point calibration method performed similarly, yielding an R2 value of 0.9956. The findings of this study indicate that competitive results in temperature sensor calibration can be achieved without circuit trimming, offering a viable alternative or a complementary approach to traditional trimming techniques