Architecture and Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures

International audienceA small area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is presented as a solution for the Dynamic Voltage and Frequency Scaling (DVFS) circuitry in Globally Asynchronous Locally Synchronous (GALS) architectures implemented in 32 nm CMOS technology. The DFLL control is designed so that the closed-loop system is able to cope with process variability while it rejects temperature changes and supply voltage slow variations. Therefore the DFLL is made of three main blocks, namely a Digitally Controlled Oscillator (DCO), a "sensor" that measures the frequency of the signal at the output of the DCO and a controller. A strong emphasis is set on the loop filter architecture choice and the tuning of its parameters. An analytical model of the DCO is deduced from accurate Spice simulations. The delay introduced by the sensor is also taken into account to design. From these models, an optimal and robust controller with a minimum implementation area is developed. Here, "optimal" means that the controller is computed via the minimization of a given criterion while the "robustness" capability ensures that the closed-loop system is tolerant to process and temperature variations in a given range. Therefore, performances of the closed-loop system are ensured whatever the system characteristics are in a given range

Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications

Internet of Things (IoT) devices such as wearable health monitors, augmented reality goggles, home automation, smart appliances, etc. are a trending topic of research. Various IoT products are thriving in the current electronics market. The IoT application needs such as portability, form factor, weight, etc. dictate the features of such devices. Small, portable, and lightweight IoT devices limit the usage of the primary energy source to a smaller rechargeable or non-rechargeable battery. As battery life and replacement time are critical issues in battery-operated or partially energy-harvested IoT devices, ultra-low-power (ULP) system on chips (SoC) are becoming a widespread solution of chip makers’ choice. Such ULP SoC requires both logic and the embedded static random access memory (SRAM) in the processor to operate at very low supply voltages. With technology scaling for bulk and FinFET devices, logic has demonstrated to operate at low minimum operating voltages (VMIN). However, due to process and temperature variation, SRAMs have higher VMIN in scaled processes that become a huge problem in designing ULP SoC cores. This chapter discusses the latest published circuits and architecture techniques to minimize the SRAM VMIN for scaled bulk and FinFET technologies and improve battery life for ULP IoT applications

Low-voltage continuous-time linear equalizer for digital video applications

This thesis presents a low-voltage continuous-time linear equalizer for the digital video application of 1080p HD video with a data rate of 3 Gbps. The equalizer was designed in the CMOS 45 nm technology with a supply voltage of 1V and bias current of 1.5 mA. The equalizer has a variable gain, which can be adjusted to suit the cable length and physical parameters. The circuit design of the equalizer filter includes a 3-stage filter, where each stage has been implemented as a variable gain amplifier along with a linear transconductance amplifier as a gain control stage. The equalizer is capable of compensating for the loss of a coaxial cable within the range 0-240 m in length, with each stage compensating for a cable of 80 m. The circuit design of the equalizer was implemented in the CMOS 45 nm technology in Cadence Virtuoso. The equalizer was also tested in Matlab, using the model of the coaxial cable to demonstrate the equalization of the data. The transient results of the equalized data, as well as the eye diagrams, are presented in this work

Ultra-Low-Power Wake-up Clock Design for SoC Applications

This thesis studies how to design an ultra-low-power wake-up clock circuit for SoCapplications that essentially consists of a resistor based reference circuit, switched-capacitor branch, an ultra-low-power amplifier, a VCO and a non-overlapping clockphase generator circuit. The circuit is designed in 180-nm CMOS technology usingCAD software for circuit design, layout design, pre and post-layout simulations.At first, a brief study of different clock-generation circuit architectures is made,wherein their merits and de-merits are discussed. This is followed by a study ofan ultra-low-power amplifier, ring-oscillator-based VCO, non-overlapping clockcircuits, the bias generation circuit and the current reference circuit. Additionally,a reference current chopping technique that further improves temperature stabilityis also described. Later, the report discusses the design and simulations of theactual implementation. Analysis of the design with regards to power consumption,temperature stability and layout area are carried out. The circuit operates at8.254kHz consuming 70.4nW with a temperature stability of 7.35ppm/◦C in thetemperature range of -40◦C to 75◦C. The final layout takes an area of 0.153mm2.The final design is analysed for its functionality at various process, voltage andtemperature corners. Future improvements in the current design are also discussedat the end of this report

An Investigation of Ultra-Wideband Filters for Cognitive Radio Networks

The requirement for radio spectrum has been increasing and this has resulted in the materialization of wireless applications with enhanced features and higher data rate. The spectrum is scant, and the current radio spectrum regulation is making its use inefficient. This necessitates the development of new dynamic spectrum allocation policies to better exploit the existing spectrum. According to the present spectrum allocation regulations, specific frequency bands are allocated to particular services and only approved users are granted access to licensed bands. Cognitive radio (CR) is expected to modernize the mode spectrum is allocated. In a CR network, the intelligent radio part allows secondary users (unlicensed users) to access spectrum bands allocated to the licensed primary users with the avoidance of interference. A solution to this inefficiency has been highly successful in the ISM (2.4 GHz), the U-NII (5–6 GHz), and microwave (57–64 GHz) bands, by making the unused spectra accessible on an unlicensed basis. However, in order to obtain spectra for unlicensed operation, new sharing concepts have been introduced to allow the usage of spectra by secondary users under the prerequisite that they limit their interference to the primary users. This would start by studying techniques employed in the design of UWB filters. This study is aimed to investigate the filters for overlay and underlay CR. This paper presents a comparative study of ultra-wideband filters for Cognitive Radio Networks

WIRELESS SENSOR NODE WITH LOW-POWER SENSING

Wireless sensor network consists of a large number of simply sensor nodes that collect information from the external environment by sensors, process the information, and communicate with other neighboring nodes in the network. Usually sensor nodes operate with exhaustible batteries unattended. Since manual replacement or recharging the batteries is not an easy, desirable and always possible task, the power consumption becomes a very important issue in the development of these networks. The total power consumption of a node is a result of all steps of operation: sensing, data processing and radio transmission. In this work we focus on the impact of sensing hardware on the total power consumption of a sensor node. Firstly, we describe the structure of sensor node architecture, identify its key energy consumption sources, and introduce an energy model for the sensing subsystem as building block of a node. Secondly, with aim to reduce energy consumption of a node we propose implementation of two power-saving techniques: duty-cycling and power-gating. Duty-cycling is effective at system level. It is used for switching a node between active and sleep mode (with duty-cycle factor of 1% reduction of in dynamic energy consumption is achieved). Power-gating is implemented at circuit level with goal to decrease a power loss due to leakage current (in our design, a reduction of dynamic and static energy consumption of off-chip sensor elements as constituents of sensing hardware within a node of is achieved). Our MATLAB simulation results suggest that in total for a sensing hardware thanks to involving of duty-cycling and power-gating secures a three order of magnitude reduction ( ) in energy consumption can be achieved compared to a node architecture in which the implementation of  both energy saving techniques are omitted

Energy-Efficient Wireless Connectivity and Wireless Charging For Internet-of-Things (IoT) Applications

During the recent years, the Internet-of-Things (IoT) has been rapidly evolving. It is indeed the future of communication that has transformed Things of the real world into smarter devices. To date, the world has deployed billions of “smart” connected things. Predictions say there will be 10’s of billions of connected devices by 2025 and in our lifetime we will experience life with a trillion-node network. However, battery lifespan exhibits a critical barrier to scaling IoT devices. Replacing batteries on a trillion-sensor scale is a logistically prohibitive feat. Self-powered IoT devices seems to be the right direction to stand up to that challenge. The main objective of this thesis is to develop solutions to achieve energy-efficient wireless-connectivity and wireless-charging for IoT applications. In the first part of the thesis, I introduce ultra-low power radios that are compatible with the Bluetooth Low-Energy (BLE) standard. BLE is considered as the preeminent protocol for short-range communications that support transmission ranges up to 10’s of meters. Number of low power BLE transmitter (TX) and receiver (RX) architectures have been designed, fabricated and tested in different planar CMOS and FinFET technologies. The low power operation is achieved by combining low power techniques in both the network and physical layers, namely: backchannel communication, duty-cycling, open-loop transmission/reception, PLL-less architectures, and mixer-first architectures. Further novel techniques have been proposed to further reduce the power the consumption of the radio design, including: a fast startup time and low startup energy crystal oscillators, an antenna-chip co-design approach for quadrature generation in the RF path, an ultra-low power discrete-time differentiator-based Gaussian Frequency Shift Keying (GFSK) demodulation scheme, an oversampling GFSK modulation/demodulation scheme for open loop transmission/reception and packet synchronization, and a cell-based design approach that allows automation in the design of BLE digital architectures. The implemented BLE TXs transmit fully-compliant BLE advertising packet that can be received by commercial smartphone. In the second part of the thesis, I introduce passive nonlinear resonant circuits to achieve wide-band RF energy harvesting and robust wireless power transfer circuits. Nonlinear resonant circuits modeled by the Duffing nonlinear differential equation exhibit interesting hysteresis characteristics in their frequency and amplitude responses that are exploited in designing self-adaptive wireless charging systems. In the magnetic-resonance wireless power transfer scenario, coupled nonlinear resonators are proposed to maintain the power transfer level and efficiency over a range of coupling factors without active feedback control circuitry. Coupling factor depends on the transmission distance, lateral, and angular misalignments between the charging pad and the device. Therefore, nonlinear resonance extends the efficient charging zones of a wireless charger without the requirement for a precise alignment.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/169842/1/omaratty_1.pd

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively