A 3.125 Gb/s 5-TAP CMOS Transversal Equalizer

Recently, there is growing interest in high speed circuits for broadband communication, especially in wired networks. As the data rate increases beyond 1 GB/s conventional materials used as communication channels such as PCB traces, coaxial cables, and unshielded twisted pair (UTP) cables, etc. attenuate and distort the transmitted signal causing bit errors in the receiver end. Bit errors make the communication less reliable and in many cases even impossible. The goal of this work was to analyze, and design an channel equalizer capable of restoring the received signal back to the original transmitted signal. The equalizer was designed in a standard CMOS 0.18 µm process and it is capable of compensating up to 20 dB’s of attenuation at 1.5625 GHz for 15 and 20 meters of RG-58 A/U coaxial cables. The equalizer is able to remove 0.5 UI ( 160 ps ) of peak-to-peak jitter and output a signal with 0.1 UI ( 32 ps ) for 15 meters of cable at 3.125 Gb/s. The equalizer draws 18 mA from a 1.8 V power supply which is lower than publications [1, 2] for CMOS transversal equalizers

Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology

This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz

Asynchronous data-dependent jitter compensation

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 95-96).Data-dependent jitter (DDJ) caused by lossy channels is a limiting factor in the bit rates that can be achieved reliably over serial links. This thesis explains the causes of DDJ and existing equalization techniques, then develops an asynchronous (clock-agnostic) architecture for DDJ compensation. The compensation circuit alters the transition times of a digital signal to cancel the expected channel-induced delays. It is designed for a 0.35 [mu]m BiCMOS process with a 240 x 140 ¹m footprint and typically consumes 3.4 mA, a small fraction of the current used in a typical transmitter. Extensive simulations demonstrate that the circuit has the potential to reduce channel-induced DDJ by at least 50% at bit rates of 6.25 Gb/s and 10 Gb/s.by Michael Price.M.Eng

シリコンフォトニクスを用いた高速・高感度光受信器に関する研究

Tohoku University山田　博仁課

Design Techniques for High Pin Efficiency Wireline Transceivers

While the majority of wireline research investigates bandwidth improvement and how to overcome the high channel loss, pin efficiency is also critical in high-performance wireline applications. This dissertation proposes two different implementations for high pin efficiency wireline transceivers. The first prototype achieves twice pin efficiency than unidirectional signaling, which is 32Gb/s simultaneous bidirectional transceiver supporting transmission and reception on the same channel at the same time. It includes an efficient low-swing voltage-mode driver with an R-gm hybrid for signal separation, combining the continuous-time-linear-equalizer (CTLE) and echo cancellation (EC) in a single stage, and employing a low-complexity 5/4X CDA system. Support of a wide range of channels is possible with foreground adaptation of the EC finite impulse response (FIR) filter taps with a sign-sign least-mean-square (SSLMS) algorithm. Fabricated in TSMC 28-nm CMOS, the 32Gb/s SBD transceiver occupies $0.09 mm^{2}$ area and achieves 16Gb/s uni-directional and 32Gb/s simultaneous bi-directional signals. 32Gb/s SBD operation consumes 1.83mW/Gb/s with 10.8dB channel loss at Nyquist rate. The second prototype presents an optical transmitter with a quantum-dot (QD) microring laser. This can support wavelength-division multiplexing allowing for high pin efficiency application by packing multiple high-bandwidth signals onto one optical channel. The development QD microring laser model accurately captures the intrinsic photonic high-speed dynamics and allows for the future co-design of the circuits and photonic device. To achieve higher bandwidth than intrinsic one, utilizing both techniques of optical injection locking (OIL) and 2-tap asymmetric Feed-forward equalizer (FFE) can perform 22Gb/s operation with 3.2mW/Gb/s. The first hybrid-integration directly-modulated OIL QD microring laser system is demonstrated

Design of Energy-Efficient Equalization and Data Encoding/Decoding Techniques for Wireline Communication Systems

Ever increasing global internet data traffic has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals suffering from greater channel loss and exponential increase in power consumption, mainly caused by a heavier amount of required equalization. In this dissertation, two distinct methodologies for designing SerDes transceivers are presented: 1) a pulse width modulated (PWM) time-domain feed forward equalizer (FFE) and linearity improvement technique for higher-order pulse amplitude modulation (PAM) including PAM-8, and 2) an inter-symbol interference (ISI)-resilient data encoding and decoding technique with Dicode encoding and error correction logic for low-bandwidth wireline channels, as an alternative strategy for communicating in an energy-efficient way on bandwidth-limited wireline channels without using conventional equalizers or filters. The first topic is a PAM-8 wireline transceiver with receiver-side pulse-width-modulated (PWM) or time-domain based feed forward equalization (FFE) technique. The receiver converts voltage-modulated signals or PAM signals to PWM signals and processes them using inverter based delay elements having rail to rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65 nm CMOS. The second topic is an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or filters (FFE, DFE, and CTLE): Inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation is that Dicode-encoded data have no consecutive 1s or -1s. With this known information, the error correction logic at the receiver can correct multi-bit errors due to ISI. Implemented in 65 nm CMOS, the proposed digital encoding and decoding approach can achieve BER less than 10−12 while communicating on a channel with an insertion loss of 24.2 dB and 21.4 dB with 2.56 pJ/bit and 2.66 pJ/bit efficiency while operating at 13.6 Gb/s and 16 Gb/s, respectively

Silicon photonic modulators for PAM transmissions

High-speed optical interconnects are crucial for both data centers and high performance computing systems. High power consumption and limited device bandwidth have hindered the move to higher optical transmission speeds. Integrated optical transceivers in silicon photonics (SiP) using pulse-amplitude modulation (PAM) are a promising solution to increase data rates. In this paper, we review recent progress in SiP for PAM transmissions. We focus on materials and technologies available CMOS-compatible photonics processes. Performance metrics of SiP modulators and crucial considerations for high-speed PAM transmissions are discussed. Various driving strategies to achieve optical PAM signals are presented. Some of the state-of-the-art SiP PAM modulators and integrated transmitters are reviewed

Analysis and Design of High Speed Serial Interfaces for Automotive Applications

The demand for an enriched end-user experience and increased performance in next generation electronic applications is never ending, and it is a common trend for a wide spectrum of applications owing to different markets, like computing, mobile communication and automotive. For this reason High Speed Serial Interface have become widespread components for nowadays electronics with a constant demand for power reduction and data rate increase. In the frame of gigabit serial systems, the work discussed in this thesis develops in two directions: on one hand, the aim is to support the continuous data rate increase with the development of novel link modeling approaches that will be employed for system level evaluation and as support in the design and characterization phases. On the other hand, the design considerations and challenges in the implementation of the transmitter, one of the most delicate blocks for the signal integrity performance of the link, are central. The first part of the activity regarding link performance predictions lead to the development of an enhanced statistical simulation approach, capable to account for the transmitter waveform shape in the ISI analysis, a characteristic that is missed by the available state-ofthe- art simulation approaches. The proposed approach has been extensively tested by comparison with traditional simulation approaches (Spice-like simulators) and validated against experimental characterization of a test system, with satisfactory results. The second part of the activity consists in the design of a high speed transmitter in a deeply scaled CMOS technology, spanning from the concept of the circuit, its implementation and characterization. Targets of the design are to achieve a data rate of 5 Gb/s with a minimum voltage swing of 800 mV, thus doubling the data rate of the current transmitter implementation, and reduce the power dissipation adopting a voltage mode architecture. The experimental characterization of the fabricated lot draws a twofold picture, with some of the performance figures showing a very good qualitative and quantitative agreement with pre-silicon simulations, and others revealing a poor performance level, especially for the eye diagram. Investigation of the root causes by the analysis of the physical silicon design, of the bonding scheme of the prototypes and of the pre-silicon simulations is reported. Guidelines for the redesign of the circuit are also given.Nel panorama delle applicazioni elettroniche il miglioramento delle performance di un prodotto da una generazione alla successiva ha lo scopo di offrire all\u2019utilizzatore finale nuove funzioni e migliorare quelle esistenti. Negli ultimi anni grazie al costante avanzamento della tecnologia integrata, si \ue8 assistito ad un enorme sviluppo della capacit\ue0 computazionale dei dispositivi in tutti i segmenti di mercato, quali ad esempio l\u2019information technology, la comunicazione mobile e l\u2019automotive. La conseguente necessit\ue0 di mettere in comunicazione dispostivi diversi all\u2019interno della stessa applicazione e di traferire grosse quantit\ue0 di dati ha provocato una capillare diffusione delle interfacce seriali ad alta velocit\ue0, o High Speed Serial Interfaces (HSSIs). La necessit\ue0 di ridurre il consumo di potenza e aumentare il bit rate per questo tipo di applicazioni \ue8 diventata dunque un ambito di ricerca di estremo interesse. Il lavoro discusso in questa tesi si colloca nell\u2019ambito della trasmissione di dati seriali a bit rate superiori ad 1Gb/s e si sviluppa in due direzioni: da un lato, a sostegno del continuo aumento del bit rate nelle nuove generazioni di interfacce, \ue8 stato affrontato lo sviluppo di nuovi approcci di modellazione del sistema, che possano essere impiegati nella valutazione delle prestazioni dell\u2019interfaccia e a supporto delle fasi di progettazione e di caratterizzazione. Dall\u2019altro lato, si \ue8 focalizzata l\u2019attenzione sulle sfide e sulle problematiche inerenti il progetto di uno dei blocchi pi\uf9 delicati per le prestazioni del sistema, il trasmettitore. La prima parte della tesi ha come oggetto lo sviluppo di un approccio di simulazione statistico innovativo, in grado di includere nell\u2019analisi degli effetti dell\u2019interferenza di intersimbolo anche la forma d\u2019onda prodotta all\u2019uscita del trasmettitore, una caratteristica che non \ue8 presente in altri approcci di simulazione proposti in letteratura. La tecnica proposta \ue8 ampiamente testata mediante il confronto con approcci di simulazione tradizionali (di tipo Spice) e mediante il confronto con la caratterizzazione sperimentale di un sistema di test, con risultati pienamente soddisfacenti. La seconda parte dell\u2019attivit\ue0 riguarda il progetto di un trasmettitore integrato high speed in tecnologia CMOS a 40nm e si estende dallo studio di fattibilit\ue0 del circuito fino alla sua realizzazione e caratterizzazione. Gli obiettivi riguardano il raggiungimento di un bit rate pari a 5 Gb/s, raddoppiando cos\uec il bit rate dell\u2019attuale implementazione, e di una tensione differenziale di uscita minima di 800mV (picco-picco) riducendo allo stesso tempo la potenza dissipata mediante l\u2019adozione di una architettura Voltage Mode. I risultati sperimentali ottenuti dal primo lotto fabbricato non delineano un quadro univoco: alcune performance mostrano un ottimo accordo qualitativo e quantitativo con le simulazioni pre-fabbricazione, mentre prestazioni non soddisfacenti sono state ottenute in particolare per il diagramma ad occhio. Grazie all\u2019analisi del layout del prototipo, del bonding tra silicio e package e delle simulazioni pre-fabbricazione \ue8 stato possibile risalire ai fattori responsabili del degrado delle prestazioni rispetto alla previsioni pre-fabbricazione, permettendo inoltre di delineare le linee guida da seguire nella futura progettazione di un nuovo prototipo

Wireless Channel Modeling For Networks On Chips

The advent of integrated circuit (chip) multiprocessors (CMPs) combined with the continuous reduction in device physical size (technology scaling) to the sub-nanometer regime will result in an exponential increase in the number of processing cores that can be integrated within a single chip. Today’s CMPs already support tens to low hundreds of cores and both industry and academic roadmaps project that future chips will have thousands of cores. Therefore, while there are open questions on how to harness the computing power offered by CMPs, the design of power-efficient and compact on-chip interconnection networks that connects cores, caches and memory controllers has become imperative for sustaining the performance of CMPs. As the limited scalability of bus-based networks degrades performance by reducing data rates and increasing latency, the Network-on-Chip (NoC) design paradigm has gained momentum, where a network of routers and links connects all the cores. However, power consumption of NoCs is a significant challenge that should be addressed to capitalize on the scaling advantages of multicores. Also, improvements in metal wire characteristics will no longer satisfy the power and performance requirements of on-chip communication. One approach to continue the performance improvements is to integrate new emerging technologies into the electronic design flow such as wireless/RF technologies, since they provide unique advantages that make them desirable in a NoC environment. First, wireless technologies are ubiquitous and offer a wide range of options in communication, and there exists a vast body of knowledge for the design and implementation of wireless chipsets using RF-CMOS technology. Second, wireless communication, unlike wired transmission, can be omnidirectional, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Third, wireless communication can increase the communication data rate by the combination of Frequency Division Multiplexing (FDM) and Time Division Multiplexing (TDM) (and in the future, potentially spatial division multiplexing (SDM)). Therefore, Wireless NoC (WiNoC) interconnects have recently emerged as a viable solution to mitigate power concerns in the short to medium term while still providing competitive performance metrics, i.e., low power consumption, tens of Gbps data rates, and minimal circuit area (or volume) within the chip. Worth noting is that wireless links are not envisioned as replacing all wired links, but rather as augmenting the wired interconnection network. In this dissertation, we employ simulations in HFSS from Ansys® to present accurate wireless channel models for a realistic WiNoC environment. We investigate the performance of these models with different types of narrowband and wideband antennas. This entails estimation of the scattering parameters for the channels between multiple antenna elements in the WiNoC, from which we derive channel transfer functions and channel impulse responses. Using these results, we can estimate the throughput of the various WiNoC links, and this allows us to design effective multiple access (MA) schemes via FDM and TDM. For these MA schemes, we provide estimates of maximal throughput. To further the feasibility study, we investigate the performance of a simple binary transmission scheme--On-Off Keying (OOK)--through the resulting dispersive channels, which can facilitate one-hop unicast, multicast, and broadcast communication that can result in a reduction in power consumption while allowing for faster communication. Our investigation of the performance of On-Off Keying modulation (OOK) also includes an analytical expression for bit error ratio (BER) that can be evaluated numerically. This enables us to provide the equalization requirements needed to achieve our target BERs. Finally, we provide recommendations for WiNoC design and future tasks related to this research

Design of High-Speed SerDes Transceiver for Chip-to-Chip Communications in CMOS Process

With the continuous increase of on-chip computation capacities and exponential growth of data-intensive applications, the high-speed data transmission through serial links has become the backbone for modern communication systems. To satisfy the massive data-exchanging requirement, the data rate of such serial links has been updated from several Gb/s to tens of Gb/s. Currently, the commercial standards such as Ethernet 400GbE, InfiniBand high data rate (HDR), and common electrical interface (CEI)-56G has been developing towards 40+ Gb/s. As the core component within these links, the transceiver chipset plays a fundamental role in balancing the operation speed, power consumption, area occupation, and operation range. Meanwhile, the CMOS process has become the dominant technology in modern transceiver chip fabrications due to its large-scale digital integration capability and aggressive pricing advantage. This research aims to explore advanced techniques that are capable of exploiting the maximum operation speed of the CMOS process, and hence provides potential solutions for 40+ Gb/s CMOS transceiver designs. The major contributions are summarized as follows. A low jitter ring-oscillator-based injection-locked clock multiplier (RILCM) with a hybrid frequency tracking loop that consists of a traditional phase-locked loop (PLL), a timing-adjusted loop, and a loop selection state-machine is implemented in 65-nm C-MOS process. In the ring voltage-controlled oscillator, a full-swing pseudo-differential delay cell is proposed to lower the device noise to phase noise conversion. To obtain high operation speed and high detection accuracy, a compact timing-adjusted phase detector tightly combined with a well-matched charge pump is designed. Meanwhile, a lock-loss detection and lock recovery is devised to endow the RILCM with a similar lock-acquisition ability as conventional PLL, thus excluding the initial frequency set- I up aid and preventing the potential lock-loss risk. The experimental results show that the figure-of-merit of the designed RILCM reaches -247.3 dB, which is better than previous RILCMs and even comparable to the large-area LC-ILCMs. The transmitter (TX) and receiver (RX) chips are separately designed and fab- ricated in 65-nm CMOS process. The transmitter chip employs a quarter-rate multi-multiplexer (MUX)-based 4-tap feed-forward equalizer (FFE) to pre-distort the output. To increase the maximum operating speed, a bandwidth-enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. The receiver chip employs a two-stage continuous-time linear equalizer (CTLE) as the analog front-end and integrates an improved clock data recovery to extract the sampling clocks and retime the incoming data. To automatically balance the jitter tracking and jitter suppression, passive low-pass filters with adaptively-adjusted bandwidth are introduced into the data-sampling path. To optimize the linearity of the phase interpolation, a time-averaging-based compensating phase interpolator is proposed. For equalization, a combined TX-FFE and RX-CTLE is applied to compensate for the channel loss, where a low-cost edge-data correlation-based sign zero-forcing adaptation algorithm is proposed to automatically adjust the TX-FFE’s tap weights. Measurement results show that the fabricated transmitter/receiver chipset can deliver 40 Gb/s random data at a bit error rate of 16 dB loss at the half-baud frequency, while consuming a total power of 370 mW