DESIGN OF A CHARGE-PUMP PHASE-LOCKED LOOP USED FOR SERDES TRANSRECEIVER

近年来由于计算机处理速度和网路的快速发展，电子工业界兴起了一股向数据传输和高速串行数据通信研究的热潮。传统并行接口技术已无法满足数据传输数率的进一步提高，过去主要用于光纤通信的串行通信技术—SerDes正逐步取代传统并行总线而成为高速接口技术的主流。 SerDes是一种时分多路复用（TMD）、点对点的通信技术，即在发送端多路低速并行信号被转换为高速串行信号，经过传输线，最后在接收端高速串行信号重新转换成低速并行信号。这种串行技术充分利用传输媒体的信道容量，减少所需的传输信道和器件引脚数，从而大大降低了通信成本。本论文实现了一款用于SerDes接口发送端和接收端的电荷泵锁相环，将25MHz到8...Under the development of the network and computer operator speed in recent years, a trend of data transmission and study at high-speed serial communication is growing. The conventional parallel bus interface technology is unable to meet the increasing speed of data transmission. Serial link interface used in optical fiber communication in the past ---SerDes is replacing gradually the conventional ...学位：工学硕士院系专业：物理与机电工程学院物理学系_微电子学与固体电子学学号：1982007115231

Design of A Low Frequency Charge-Pump PLL Frequency Synthesizer

近年来D类功率放大器凭借其高效率、低功耗、体积小等特点，广泛地应用于小型便携式音频设备中。它采用脉冲宽度调制（PWM）技术来实现音频信号的放大。而作为脉冲宽度调制技术所必须的三角波信号的性能很大程度上影响着功放的性能。电荷泵锁相环频率合成器（CPPLL）凭借其频谱纯、稳定性高、体积小等特点成为了频率合成器发展的主要方向，并广泛地应用于通信、计算机等领域。本文将设计一款电荷泵锁相环频率合成器，使其产生D类功率放大器所需要的低频三角波信号。 在介绍了锁相环基本原理，比较各模块电路性能的基础上，本文设计的可编程电荷泵锁相环频率合成器主要包括鉴频鉴相器、电荷泵、低通滤波器以及压控振荡器。其中鉴频鉴相...In recent years, Class D power amplifiers are widely used in small-scale portable audio devices because of its high efficiency, low power consumption and smaller size etc.. It is based on the pulse width modulation (PWM) technology to realize the audio signal amplification. The characteristic of the triangular wave which is the important part of the PWM technology has a large extent affect on the ...学位：工学硕士院系专业：物理与机电工程学院_电子与通信工程学号：1982011115288

Design of low-frequency charge pump PLL

设计一款音频范围内的电荷泵锁相环,采用动态d触发器鉴频鉴相器及电流舵差分输入电荷泵。压控振荡器采用了对电容充放电的形式产生震荡波形,实现低频输出。采用HHnEC bCd035工艺并用CAdEnCE软件实现仿真,实现250 kHz频率锁定,锁定时间为80μS,锁定时相位差为75 nS且压控振荡器控制电压纹波为5 MV。A charge pump PLL working in audio frequency was designed,in which a TSPC-PFD and a current steering charge pump were used.In order to get the low frequency,a VCO that get the output wave by charging or discharging the capacity is used.The circuit is designed with HHNEC BCD035 process and the behavior is simulated with Cadence.The locking frequency of 250 kHz was achieved.Its locking time is 80 μs.when it is locked,the phase difference is 75 ns,and the ripple of the VCO control voltage is 5 mV

Design of a Charge-pump Phase-locked Loop Frequency Synthesizer used for Bluetooth communications

锁相环是模拟及数模混合电路中一个基本的并且非常重要的模块，是一个能实现自动跟踪的反馈系统。它跟踪参考信号，自动校正输出信号的频差和相差，实现时钟的同步。本文研究和设计了一种应用于蓝牙通信系统的电荷泵锁相环频率合成器，其工作频段是2.402-2.480GHz，分为79个信道。整个频率合成器主要包括鉴频鉴相器、电荷泵、滤波器、压控振荡器、预分频器和分频器等等。锁相环的设计涉及到信号与系统、微电子学、半导体工艺学和测试等方面，设计难度较大。鉴于锁相环在蓝牙通信中的重要性和设计的挑战性，研究和设计锁相环很具现实意义，也是非常必要的。 论文首先介绍频率合成技术和发展，以及频率合成器的性能指标，然后分析...As a fundamental and very important building block in analog and mixed-signal integrated circuit, phase-locked loop (PLL) is an auto-tracking feedback system, which can track the reference signal and regulate the different of input signals frequency and phase automatically in order to realize the synchronization of clock. This paper presents the design of a charge-pump phase-locked loop (PLL) freq...学位：工学硕士院系专业：物理与机电工程学院物理学系_物理电子学学号：1982007115229

Design of Carrier Synchronization Based on Costas Loop

介绍了平方变换法相干解调原理,从工程角度完善了载波提取的电路结构,消除了频移载波的误锁问题.提出用科斯塔斯环法来实现从2dPSk信号中提取相干载波,解决了提取的载波信号存在180度的相位含糊问题,为通信系统提高抗噪性能提供了条件.当载波频率很高时,工作频率较低的科斯塔斯环易于实现.并用SIMulInk设计出科斯塔斯环法提取载波的仿真电路图和进行相应的仿真实验.Theory of coherent demodulation based on method of square counterchange is introduced in this article.The structure of circuit for carrier recovery is perfected in engineering,and the problem of error-lock for frequency-shift carrier is eliminated.Costas Loop is put forward to achieve coherent carrier from 2DPSK signal in this article.The 180° phase's inexplicit problem which exist in carrier recovery is resolved.It improves the resisting noise property of communication system.When carrier frequency is higher,Costas loop is easy to implement carrier synchronization.Because the operating frequency of Costas loop is lower than square PLL.We scheme out emulational circuit diagram for carrier distilling with Costas loop by using simulink and process corresponding emulational experiment.国家自然科学基金项目(60873179);广西教育厅科研项目(200707LX196

Research and Design of CMOS Wideband Frequency Synthesizer

随着宽带无线技术的发展，通信系统对频率源提出了更高的要求，频率合成技术是人们获得可控频率源的主要途径，该技术的载体——频率合成器，是通信系统中的核心模块及决定通信质量的关键因素。 本文系统地分析了锁相环频率合成及∑-Δ调制技术的原理，并通过Verilog\Verilog-A对∑-Δ小数频率合成器进行系统行为级建模，以此分析模块参数对系统动态特性的影响，并借助该模型加速设计中仿真的速度。文中通过使用25bitMASH1-1-1∑-Δ调制器，实现了小于2Hz的输出频率分辨率；并引入了基于环形振荡原理的伪随机数发生器，有效地降低了∑-Δ调制器的量化噪声；通过在鉴频鉴相器-电荷泵系统引入分流支路，最...As the development of wideband wireless technology, the demand of frequency source is much stricter in communication system. Frequency synthesis technology is the major method to get a controllable frequency source. Frequency synthesizer, which is the realization of frequency synthesis technology, is a main building block in communication system and the key factor of communication quality. In ...学位：工学硕士院系专业：物理与机电工程学院物理学系_微电子学与固体电子学学号：1982007115229

Design and Application of Monolithic Integrated Clock Circuit

时钟电路是数模混合集成电路及数字集成电路的重要模块，广泛应用于SoC、MCU等微系统中，时钟电路的质量好坏直接影响到该系统性能的稳定与否。目前广泛采用石英晶体振荡器结合锁相环产生时钟信号，石英晶振拥有优越的电压和温度的特性，能够稳定地工作，但是难以集成到芯片内部，且附加了器件成本，阻碍了芯片的高度集成化。 文章系统地分析了时钟电路的基本原理，应用MATLAB/Verilog-A对包含参考时钟源电路和锁相环路的整个时钟电路进行行为级的建模和仿真，通过建模仿真分析电路的各个参数间的折衷关系。对于参考时钟源，文章采用无需晶振的片内环形振荡器结构实现了参考时钟源的可集成性，并提出高阶温度补偿方案，使...Clock circuit is an important module in mixed-signal/digital-signal integrated circuit, and it is widely used in microsystems such as SoC and MCU. The quality of the clock circuit has a direct influence on the performance of the system stability. It is widely using quartz crystal oscillator combined with the phase-lock loop to generate clock signal. Quartz crystal oscillator has the superior volta...学位：工学硕士院系专业：信息科学与技术学院电子工程系_微电子学与固体电子学学号：2312009115268

基于跳频技术的GPS移动通信网和CATV加解扰系统的研究

本文从公安系统110指挥中心全球卫星定位移动车辆监控系统GPSAVL 目前存在的问题出发提出在原有GPSAVL系统的基础上加以改进综合跳频 FH通信码分多址CDMA时分多址TDMA等多种技术采用新型小 区制两级蜂窝组网方式和通信协议模型以满足提高车载单元与监控中心之间的 动态数据交换速率GIS电子地图的实时显示和实时报警速度扩大系统的容量和 信道的使用效率增强通信的隐蔽性保密性和抗恶意干扰抗多径衰落能力的 要求力求做到有较好的频率规划和克服远近效应的能力 对实际工程中的关键困难如跳频图案(地址编码)设计频率合成器参数的确 定跳频同步电路的构成跳频调制与解调方式的选择以及实际建网...学位：理学硕士院系专业：计算机与信息工程学院电子工程系_无线电物理学号：19963000

一种增/减量可变的计数式数控振荡器的设计

数控振荡器是全数字锁相环中的关键部件,目前应用较多的是除N计数式数控振荡器和增量/减量计数式数控振荡器,应用于锁相环时,前者做一次分频比调整就能使环路进入锁定状态,捕捉时间短,后者捕捉时间长,却有着前者没有的优势:结构简单、易于集成。提出了一种增/减量可变的计数式数控振荡器电路,此电路结构简单,同时也具有捕捉时间短的优点

Carrier-current Transceiver Systems Consisted of LM1893 Carrier-current Transceiver IC

电力线载波通信系统利用电力线来实现远程数据传送 .L M1893是一种可完成串行数据半双工通信 ,具有发送和接收数据的全部功能的载波通信芯片 .数据发送时 ,经过 FSK调制之后的正弦载波信号可适合现有的各种电力线路 ;数据接收时 ,差分锁相环电路和三级噪声滤波电路保证了接收数据的精度 .一个完整的载波通信系统只需 L M1893、一个控制单元和一些外部元件便可构成 .Carrier current systems use the power line mains to transfer information between remote locations. This bipolar carrier current chip performs as a power line interface for half duplex (bi directional)communication of serial bit streams of virtually any coding.In transmission, a sinusoidal carrier is FSK modulated and impressed on any power line via a rugged on chip driver.In reception,a PLL based demodulator and impulse noise filter combine to give maximum range. A complete system may consist of the LM1893, a cops controller and discrete components