Band Gap Modulated Tunnel FET

This chapter presents bandgap-modulated tunnel field effect transistor (TFET) and discusses its simulation and modeling. A geometry of TFET, the heterojunction TFET, is considered, and different electrical parameters are discussed using Technology Computer Aided Design (TCAD) tool. The effect of the heterojunction on the characteristics is observed through the variations in the length and mole fraction of the pocket layer adjacent to the source. An analytical model is further presented for gate-drain underlap TFET using 2-D Poisson equation and Kane’s interband tunneling model. The results are validated with the output from the TCAD tool

Insights into tunnel FET-based charge pumps and rectifiers for energy harvesting applications

In this paper, the electrical characteristics of tunnel field-effect transistor (TFET) devices are explored for energy harvesting front-end circuits with ultralow power consumption. Compared with conventional thermionic technologies, the improved electrical characteristics of TFET devices are expected to increase the power conversion efficiency of front-end charge pumps and rectifiers powered at sub-µW power levels. However, under reverse bias conditions the TFET device presents particular electrical characteristics due to its different carrier injection mechanism. In this paper, it is shown that reverse losses in TFET-based circuits can be attenuated by changing the gate-to-source voltage of reverse-biased TFETs. Therefore, in order to take full advantage of the TFETs in front-end energy harvesting circuits, different circuit approaches are required. In this paper, we propose and discuss different topologies for TFET-based charge pumps and rectifiers for energy harvesting applications.Peer ReviewedPostprint (author's final draft

Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs).We propose a mixed TFET\u2013MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET\u2013MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET\u2013MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions

Engineering interband tunneling in nanowires with diamond cubic or zincblende crystalline structure based on atomistic modeling

We present an investigation in the device parameter space of band-to-band tunneling in nanowires with a diamond cubic or zincblende crystalline structure. Results are obtained from quantum transport simulations based on Non-Equilibrium Green's functions with a tight-binding atomistic Hamiltonian. Interband tunneling is extremely sensitive to the longitudinal electric field, to the nanowire cross section, through the gap, and to the material. We have derived an approximate analytical expression for the transmission probability based on WKB theory and on a proper choice of the effective interband tunneling mass, which shows good agreement with results from atomistic quantum simulation.Comment: 4 pages, 3 figures. Final version, published in IEEE Trans. Nanotechnol. It differs from the previous arXiv version for the title and for some changes in the text and in the reference

Process modules for GeSn nanoelectronics with high Sn-contents

In this paper we present a systematic study of GeSn n-FETs. First, process modules such as high-k metal gate stacks and NiGeSn-metallic contacts for use as source/drain contacts are characterized and discussed. GeSn alloys of different Sn content allow the study of the capacitance-voltage (CV) and contact characteristics of both direct and indirect bandgap semiconductors. We then present GeSn n-FET devices we have fabricated. The device characterization includes temperature dependent IV characteristics. As important step towards GeSn for tunnel-FET Ge0.87Sn0.13 tunnel-diodes with negative differential resistance at reduced temperature are shown. The present work provides a base for further optimization of GeSn FET and novel tunnel FET devices

A battery-less, self-sustaining RF energy harvesting circuit with TFETs for µW power applications

This paper proposes a Tunnel FET (TFET) power management circuit for RF energy harvesting applications. In contrast with conventional MOSFET technologies, the improved electrical characteristics of TFETs promise a better behavior in the process of rectification and conversion at ultra-low power (µW) and voltage (sub-0.25 V) levels. RF powered systems can not only benefit from TFETs in front-end rectifiers by harvesting the surrounding energy at levels where conventional technologies cannot operate but also in the minimization of energy required by the power management circuit. In this work we present an energy harvesting circuit for RF sources designed with TFETs. The TFET controller emulates an adequate impedance at the output of the rectifier in order to allow maximum transfer of power from the RF source to the input of the boost converter. The output load is activated once the output capacitor reaches a voltage value of 0.5 V. The results show an efficiency boost of 89 % for an output load consuming 1 µW with an available RF power of -25 dBm.Postprint (published version

높은 전류구동능력을 위한 Si/SiGe 물질을 가지는 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 박병국.For integrated circuits with highly-scaled complementary MOS (CMOS) technology, power dissipation problem has become an important issue since power per chip continues to increases and leakage power dominates in advanced technology nodes. In order to solve power issues, the supply voltage (VDD) scaling is very essential and devices which have low leakage current are needed. Recently, many research groups have studied a tunnel field-effect transistors (tunnel FETs) which is suitable for low operating power device. Tunnel FETs have very low leakage current and small subthrehold swing (SS) at room temperature unlike CMOS because of carrier injection using tunneling. In this thesis, a novel tunnel FET with SiGe body and elevated Si drain region have been proposed. The proposed tunnel FET has larger current drivability than conventional Si tunnel FETs because it uses a narrow bandgap material for low tunneling resistance. Also, it is expected that electrical characteristics can be improved by using SiGe channel and source for n-channel as well as p-channel operation. In addition, ambipolar current that is caused by band-to-band tunneling (BTBT) between channel and drain can be suppressed by using elevated Si drain region. For obtaining fundamental electrical properties of tunnel FET with SiGe body, planar structures are firstly fabricated and analyzed with Si tunnel FET. From electrical characteristics of fabricated devices, it is observed that both n-type and p-type SiGe tunnel FETs have better switching properties than Si devices. Current saturations become faster and drive current shows 10 times more than that of Si tunnel FETs. In addition, BTBT model parameters of Si and Ge materials in fabricated devices are extracted through TCAD simulation. Extracted A and B parameters of BTBT model in Si are 4×1014 cm-1s-1 and 9.9×106 V/cm. Also, A and B parameters of Ge can be extracted as 3.1×1016 cm-1s-1 and 7.1×105 V/cm, respectively. Using calibrated model parameters, proposed tunnel FET is simulated and optimized in terms of switching properties with changing Ge contents, effect of the elevated Si drain region, short-channel effects, inverter operation, and device delay. Based on these optimized simulation results, the proposed tunnel FET is fabricated using spacer technique because it is possible to make self-aligned doping process. Key unit process is as follows: epitaxial growth for Si and SiGe materials, e-beam lithography for active-fin formation, and sidewall spacer gate formation. For n-channel and p-channel operation, fabricated tunnel FET shows the better electrical characteristics than control groups. Extracted point SS is 51.1 mV/dec for p-type tunnel FET and 87 mV/dec for n-type tunnel FET. Ambipolar current of the proposed tunnel FET is suppressed to 1/100 of that of planar SiGe tunnel FET. Also, in order to analyze current flow mechanism of tunnel FET, the electrical characteristics are measured with temperature variation. As temperature goes up, Shockley-Read-Hall and field-dependent generation are increased resulting in degradation of switching property. In current saturation region, BTBT which has low temperature sensitivity is dominant on current property. From this study, it is demonstrated that the novel tunnel FET with SiGe body and the elevated Si drain shows improved electrical performance compared with Si tunnel FET. Also, both n-type and p-type devices can obtain high current drivability and small SS without structure changes. This means that the proposed device has strong advantage in terms of implementing IC with tunnel FET. Thus, it will be one of the promising candidates for next-generation devices.Abstract i Contents iv List of Figures vi Chapter 1 1 Introduction 1 1.1 POWER ISSUES ON CMOS TECHNOLOGIES 1 1.2 TUNNEL FIELD-EFFECT TRANSISTOR (TUNNEL FET) 3 1.3 ISSUES IN TUNNEL FET 6 1.4 SCOPE OF THESIS 9 Chapter 2 11 Planar Si and SiGe tunnel FETs 11 2.1 EXPITAXY GROWTH FOR SI AND SIGE LAYERS 11 2.2 SIGE MOSCAP AND MOSFET FABRICATION 14 2.3 PLANAR SI AND SIGE TUNNEL FET 15 2.4 SUMMARY 34 Chapter 3 35 Device Simulation 35 3.1 PROPOSED TUNNEL FET 35 3.2 SIMULATION PARAMETERS AND RESULTS 37 3.3 TRANSIENT RESPONSE CHARACTERISTICS 43 Chapter 4 51 Device Characteristics 51 4.1 PROCESS FLOW 51 4.2 ACTIVE FIN PATTERNING USING E-BEAM LITHOGRAPHY 54 4.3 DRAIN AND GATE FORMATION 56 4.4 DEVICE CHARACTERISTICS 61 4.5 REASON OF DEGRADED CHARACTERISTICS IN N-TYPE DEVICE 70 Chapter 5 73 Conclusions 73 Bibliography 77 초록 78Docto