Acceleration of Graphics Algorithms by NEON Coprocessor

Cílem této práce je prozkoumat možnosti koprocesoru NEON. Porovnávají se grafické algoritmy napsané v jazyce C, jazyce symbolických adres, jazyce C s využitím intrinsických funkcí a automaticky vektorizovaný kód. Hlavním zjištěním je, že jde zkrátit délku výpočtu až 60 krát a díky tomu by bylo možné tyto algoritmy provádět v reálném čase na HD videu.The aim of this work is to examine capabilities of NEON coprocessor. Various implementations of the same algorithm are compared: language C, assembly language, language C with intinsic functions and automatically vectorized code. Main conslusion is, that computation time can be reduced up to 60 times, allowing real-time HD video processing.

High-Efficient Parallel CAVLC Encoders on Heterogeneous Multicore Architectures

This article presents two high-efficient parallel realizations of the context-based adaptive variable length coding (CAVLC) based on heterogeneous multicore processors. By optimizing the architecture of the CAVLC encoder, three kinds of dependences are eliminated or weaken, including the context-based data dependence, the memory accessing dependence and the control dependence. The CAVLC pipeline is divided into three stages: two scans, coding, and lag packing, and be implemented on two typical heterogeneous multicore architectures. One is a block-based SIMD parallel CAVLC encoder on multicore stream processor STORM. The other is a component-oriented SIMT parallel encoder on massively parallel architecture GPU. Both of them exploited rich data-level parallelism. Experiments results show that compared with the CPU version, more than 70 times of speedup can be obtained for STORM and over 50 times for GPU. The implementation of encoder on STORM can make a real-time processing for 1080p @30fps and GPU-based version can satisfy the requirements for 720p real-time encoding. The throughput of the presented CAVLC encoders is more than 10 times higher than that of published software encoders on DSP and multicore platforms

Towards Real-time High-Definition Image Snow Removal: Efficient Pyramid Network with Asymmetrical Encoder-decoder Architecture

In winter scenes, the degradation of images taken under snow can be pretty complex, where the spatial distribution of snowy degradation is varied from image to image. Recent methods adopt deep neural networks to directly recover clean scenes from snowy images. However, due to the paradox caused by the variation of complex snowy degradation, achieving reliable High-Definition image desnowing performance in real time is a considerable challenge. We develop a novel Efficient Pyramid Network with asymmetrical encoder-decoder architecture for real-time HD image desnowing. The general idea of our proposed network is to utilize the multi-scale feature flow fully and implicitly mine clean cues from features. Compared with previous state-of-the-art desnowing methods, our approach achieves a better complexity-performance trade-off and effectively handles the processing difficulties of HD and Ultra-HD images. The extensive experiments on three large-scale image desnowing datasets demonstrate that our method surpasses all state-of-the-art approaches by a large margin both quantitatively and qualitatively, boosting the PSNR metric from 31.76 dB to 34.10 dB on the CSD test dataset and from 28.29 dB to 30.87 dB on the SRRS test dataset

Optical character recognition on heterogeneous SoC for HD automatic number plate recognition system

Automatic number plate recognition (ANPR) systems are becoming vital for safety and security purposes. Typical ANPR systems are based on three stages: number plate localization (NPL), character segmentation (CS), and optical character recognition (OCR). Recently, high definition (HD) cameras have been used to improve their recognition rates. In this paper, four algorithms are proposed for the OCR stage of a real-time HD ANPR system. The proposed algorithms are based on feature extraction (vector crossing, zoning, combined zoning, and vector crossing) and template matching techniques. All proposed algorithms have been implemented using MATLAB as a proof of concept and the best one has been selected for hardware implementation using a heterogeneous system on chip (SoC) platform. The selected platform is the Xilinx Zynq-7000 All Programmable SoC, which consists of an ARM processor and programmable logic. Obtained hardware implementation results have shown that the proposed system can recognize one character in 0.63 ms, with an accuracy of 99.5% while utilizing around 6% of the programmable logic resources. In addition, the use of the heterogenous SoC consumes 36 W which is equivalent to saving around 80% of the energy consumed by the PC used in this work, whereas it is smaller in size by 95%

Multifunctional photonic integrated circuit for diverse microwave signal generation, transmission and processing

Microwave photonics (MWP) studies the interaction between microwave and optical waves for the generation, transmission and processing of microwave signals (i.e., three key domains), taking advantages of broad bandwidth and low loss offered by modern photonics. Integrated MWP using photonic integrated circuits (PICs) can reach a compact, reliable and green implementation. Most PICs, however, are recently developed to perform one or more functions restricted inside a single domain. In this paper, as highly desired, a multifunctional PIC is proposed to cover the three key domains. The PIC is fabricated on InP platform by monolithically integrating four laser diodes and two modulators. Using the multifunctional PIC, seven fundamental functions across microwave signal generation, transmission and processing are demonstrated experimentally. Outdoor field trials for electromagnetic environment surveillance along an in-service high-speed railway are also performed. The success to such a PIC marks a key step forward for practical and massive MWP implementations.Comment: 17 page